This chapter describes the tools used by photonic integrated circuit designers, in particular for those focusing on the physical implementation of the design. We begin with a discussion of process design kits (PDKs) typically provided by the fabrication foundry. This is followed by a discussion of what electronic design automation (EDA) tools offer, including a library of components, schematic capture, (schematic-driven) layout, and design rule checking. We also provide suggestions for space-efficient photonic mask layout.
Process design kit (PDK)
A process design kit is a set of documentation and data files that describe a fabrication process at a semiconductor foundry and enable the user to complete a design. A typical PDK contains: documentation including technology details, mask layout instructions, and design rules; a library of cells such as modulators, detectors, etc.; component models and/or experimental data; and design verification tools. PDKs usually contain the foundry's proprietary information and trade secrets, thus are not always openly available.
In this section, we describe a Generic Silicon Photonics (GSiP) PDK, which is implemented in Mentor Graphics (Pyxis and Calibre) and Lumerical INTERCONNECT tools and is available for download. The purpose of this kit is to demonstrate the functionality of a silicon photonics design flow implementation, with no restrictions to its distribution. This kit can be adapted for different fabrication processes, and also provides insight into what PDK and libraries available today offer [1,2].
The components of the GSiP PDK include the following.
• Fabrication process parameters, mask layer table.
• Library: a small example library of components, including fibre grating couplers; waveguides, waveguide bends, and a splitter; a ring modulator; and an electrical bond pad.
– Component symbols for schematic capture: using the provided components and/or user-provided components, circuits can be designed at the schematic level.
– Component models: the library components include circuit models implemented in Lumerical INTERCONNECT.
– Component physical layout: mask layout for components is implemented in fixed-layout cells (i.e. GDS, e.g. Y-branch splitter) and parameterized (i.e. PCells, e.g. ring modulator).
• Schematic capture: this functionality allows the designer to create a schematic of their system.