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  • Online publication date: April 2016

3 - Synthesis and Fabrication of Semiconductor Nanowires

Summary

Semiconductor nanowires can be fabricated using a variety of techniques. Techniques based on the semiconductor industry legacy of using lithography patterning and material removal methods to etch semiconductor layers into nanowires are called “top-down” fabrication techniques. A typical example is the patterning of photoresist lines on top of a silicon-on-insulator layer followed by the removal of excess silicon using a plasma etch tool in order to create silicon nanowires. Another example is the patterning of an array of “dots” on a silicon substrate and the use of plasma etching to fabricate vertical silicon columns. Techniques based on the direct epitaxial growth of a nanowire from a seeding substrate without using material removal techniques are called “bottom-up” growth techniques. The classical example is the vapor–liquid–solid (VLS) growth of silicon nanowires on a silicon substrate using gold eutectic droplets [1,2].

Top-down fabrication techniques

In this section, the more common “top-down” fabrication techniques are described. They are typically based on process steps used following the semiconductor industry legacy by combining patterning using lithography and material removal using etching tools allowing the shaping of thin semiconductor films into nanowire structures.

Horizontal nanowires

Semiconductor nanowires can be fabricated using either semiconductor-on-insulator wafers or bulk semiconductor wafers. In the case of silicon, nanowires can be made using a silicon-on-insulator (SOI) wafer. The silicon film thickness can be trimmed down to the desired value using oxidation and wet oxide strip in a buffered hydrofluoric acid (HF) solution [3,4]. The lateral dimensions of the nanowire are usually defined using e-beam lithography permitting patterning of very narrow lines [5,6,7]. Other techniques, such as the use of block copolymer self-assembly, can be used to define narrow polymer parallel lines and use them as a template for pattern transfer onto a semiconductor. Directed self-assembly of block copolymers is capable of achieving high-density patterning with critical dimensions approaching 5 nm. High-density arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA block copolymer has been demonstrated. The wires are formed with a pitch of 42 nm resulting in dense arrays (5 × 106 wires/cm) of unidirectional and isolated parallel silicon nanowires on an insulator substrate. This technique demonstrated the fabrication of nanowires with critical dimension ranging down to less than 10 nm [8,9].

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[1] Chen, K.-I.et al., “Silicon nanowire field-effect transistor-based biosensors for biomedical diagnosis and cellular recording investigation,” Nano Today, vol. 6, pp. 131–154 (2011)
[2] Wagner, R.S. and Ellis, W.C., “Vapor liquid solid mechanism of single crystal growth,” Applied Physics Letters, vol. 4, no. 5, pp. 89–90 (1964)
[3] Barraud, S., et al., “Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm,” IEEE Electron Device Letters, vol. 33, no. 11, pp. 1526–1528 (2012)
[4] Bangsaruntip, S., et al., “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” Technical Digest of International Electron Device Meeting (IEDM), pp. 297–300 (2009)
[5] Baie, X.et al., “Quantum-wire effects in thin and narrow SOI MOSFETs,” Proceedings of the IEEE International SOI Conference, pp. 66–67 (1995)
[6] Hobbs, R.G.et al., “Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography,” Journal of Vacuum Science and Technology B, vol. 30, no. 4, pp. 041602.1–7 (2012)
[7] Yu, R.et al., “Top-down process of germanium nanowires using EBL exposure of hydrogen silsesquioxane resist,” Proceedings of the 13th International Conference on Ultimate Integration on Silicon (ULIS), pp. 145–148 (2012)
[8] Farrell, R.A.et al., “Large-scale parallel arrays of silicon nanowires via block copolymer directed self-assembly,” Nanoscale, vol. 4, pp. 3228–3236 (2012)
[9] Rasappa, S.et al., “Fabrication of a sub-10 nm silicon nanowire based ethanol sensor using block copolymer lithography,” Nanotechnology, vol. 24, no. 6, p. 065503 (2013)
[10] Choi, Y.-K.et al., “Fabrication of Sub-10-nm silicon nanowire arrays by size reduction lithography,” Journal of Physical Chemistry B, vol. 107, pp. 3340–3343 (2003)
[11] Bencher, C.et al., “22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP),” Proceedings of SPIE, vol. 6924, pp. 69244E.1–7 (2008)
[12] Rooyackers, R.et al., “Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency,” Technical Digest of International Electron Device Meeting (IEDM), pp. 993–996 (2006)
[13] Cerofolini, G.F., Amato, P., Romano, E., “The multi-spacer technique: a non-lithographic technique for terascale integration,” Semiconductor Science and Technology, vol. 23, p. 075020 (2008)
[14] Ben-Jamaa, M. Haykelet al., “Complete nanowire crossbar framework optimized for the multi-spacer patterning technique,” Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES ‘09), pp. 11–16 (2009)
[15] Moon, D.-I.et al., “Investigation of silicon nanowire gate-all-around junctionless transistors built on a bulk substrate,” IEEE Transactions on Electron Devices, vol. 60, no.4, pp. 1355–1360 (2013)
[16] Huang, R.et al., “Fabrication and transport behavior investigation of gate-all-around silicon nanowire transistor from top-down approach,” ECS Transactions, vol. 22, no.1, pp. 317–326 (2009)
[17] Song, Y., et al., “Performance breakthrough in gate-all-around nanowire n- and p-type MOSFETs fabricated on bulk silicon substrate,” IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1885–1890 (2012)
[18] Jurczak, M.et al., “Silicon-on-nothing (SON) – an innovative process for advanced CMOS,” IEEE Transactions on Electron Devices, vol. 47, no. 11, pp. 2179–2187 (2000)
[19] Ernst, T.et al., “Ultra-dense silicon nanowires: a technology, transport and interfaces challenges insight,” Microelectronic Engineering, vol. 88, pp. 1198–1202 (2011)
[20] Ernst, T.et al., “3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics,” IEEE International Conference on Integrated Circuit Design and Technology and Tutorial (ICICDT), pp. 265–268 (2008)
[21] Gu, J.J.et al., “III-V gate-all-around nanowire MOSFET process technology: from 3D to 4D,” Technical Digest of International Electron Device Meeting (IEDM), pp. 529–532 (2012)
[22] Li, M.et al., “Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate,” Symposium on VLSI Technology Digest of Technical Papers, pp. 94–95 (2009)
[23] Bangsaruntip, S.et al., “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” Technical Digest of the International Electron Device Meeting (IEDM), pp. 297–230 (2009)
[24] Bangsaruntip, S.et al., “Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond,” Technical Digest of the International Electron Device Meeting (IEDM), pp. 526–529 (2013)
[25] Hung, Y.-J.et al., “Fabrication of highly ordered silicon nanowire arrays with controllable sidewall profiles for achieving low-surface reflection,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 17, no. 4, pp. 869–877 (2010)
[26] Sun, Y.et al., “Demonstration of memory string with stacked junctionless SONOS realized on vertical silicon nanowire,” Technical Digest of International Electron Device Meeting (IEDM), pp. 223–226 (2011)
[27] Sun, Y.et al., “Junctionless vertical-Si-nanowire-channel-based SONOS memory with 2-bit storage per cell,” IEEE Electron Device Letters, vol. 32, no. 6, pp. 725–727 (2011)
[28] Singh, N.et al., “Si, SiGe nanowire devices by top–down technology and their applications,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3107–3118 (2008)
[29] Zhao, X., Alamo, J. del, “Nanometer-scale vertical-sidewall reactive ion etching of InGaAs for 3-D III-V MOSFETs,” IEEE Electron Device Letters, vol. 35, no. 5, pp. 521–523 (2014)
[30] Treuting, R.G., Arnold, S.M., “Orientation habits of metal whiskers,” Acta Metallurgica, vol. 5, no. 10, p. 598 (1957)
[31] Hasan, M., Huq, M.F., Mahmood, Z.H, “A review on electronic and optical properties of silicon nanowire and its different growth techniques,” SpringerPlus, vol. 2, p. 151 (2013)
[32] Wagner, R.S., Ellis, W.C., “Vapor-liquid-solid mechanism of single crystal growth,” Applied Physics Letters, vol. 4, no. 5, pp. 89–90 (1964)
[33] Schmidt, V., Wittemann, J.V., Gösele, U., “Growth, thermodynamics, and electrical properties of silicon nanowires,” Chemical Reviews, vol. 110, no. 1, pp. 361–388 (2010)
[34] Givargizov, E.I., “Fundamental aspects of VLS growth,” Journal of Crystal Growth, vol. 31, pp. 20–30 (1975)
[35] Givargizov, E.I., Kostyuk, Y.G., “Controlled growth of oriented systems of whisker crystals,” РОСТ КРИСТАЛЛОВ (Growth of Crystals), Springer, pp. 276–283 (1975)
[36] Bootsma, G.A., Gassen, H.J., “A quantitative study on the growth of silicon whiskers from silane and germanium whiskers from germane,” Journal of Crystal Growth, vol. 10, no. 3, pp. 223–234 (1971)
[37] Islam, M.S.et al., “A novel interconnection technique for manufacturing nanowire devices,” Applied Physics A, vol. 80, pp. 1133–1140 (2005)
[38] Oh, J.Y.et al., “Demonstration of gate-all-around FETs based on suspended CVD-grown silicon nanowires,” Proceedings of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (2013)
[39] Quitoriano, N.J., Kamins, T.I., “Integratable nanowire transistors,” Nano Letters, vol. 8, no 12, pp. 4410–4414 (2008)
[40] Whang, S.J.et al., “Complementary metal-oxide-semiconductor compatible Al-catalyzed silicon nanowires: growth and the effects of surface oxidation of Al seeding layer,” Electrochemical and Solid-State Letters, vol. 10, no. 6, pp. E11–E13 (2007)
[41] Kamins, T.I.et al., “Ti-catalyzed Si nanowires by chemical vapor deposition: Microscopy and growth mechanisms,” Journal of Applied Physics, vol. 89, no. 2, pp. 1008–1016 (2001)
[42] Rathi, S.J.et al., “Tin-catalyzed plasma-assisted growth of silicon nanowires,” Journal of Physical Chemistry C, vol. 115, pp. 3833–3839 (2011)
[43] Mandl, B.et al., “Growth mechanism of self-catalyzed group III-V nanowires,” Nano Letters, vol. 10, pp. 4443–4449 (2010)
[44] Sasaki, S.et al., “Encapsulated gate-all-around InAs nanowire field-effect transistors,” Applied Physics Letters, vol. 103, pp. 213502(1–5) (2013)
[45] Mårtensson, T.et al., “Epitaxial growth of indium arsenide nanowires on silicon using nucleation templates formed by self-assembled organic coatings,” Advanced Materials, vol. 19, no. 14, pp. 1801–1806 (2007)
[46] Rehnstedt, C.et al., “Vertical InAs nanowire wrap gate transistors on Si substrates,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3037–3041 (2008)
[47] Tomioka, K., Motohisa, J., Hara, S., Fukui, T., “Control of InAs nanowire growth directions on Si,” Nano Letters, vol. 8, no. 10, pp. 3475–3480 (2008)
[48] Tanaka, T.et al., “Vertical surrounding gate transistors using single InAs nanowires grown on Si substrates,” Applied Physics Express, vol. 3, pp. 025003.1–3 (2010)
[49] Goulding, M.R., “The selective epitaxial growth of silicon,” Material Science and Engineering B, Solid State Materials for Advanced Technology, vol. 17, no. 1–3, pp. 47–67 (1993)
[50] Cheong, W.-S., “Optimization of selective epitaxial growth of silicon in LPCVD,” ETRI Journal, vol. 25, no. 6, pp. 503–509 (2003)
[51] Iacopi, F.et al., “Seedless templated growth of hetero-nanostructures for novel microelectronics devices,” Materials Research Society (MRS) Proceedings, vol. 1178 (2009), http://dx.doi.org/10.1557/PROC-1178-AA04-04
[52] Wernersson, L.-E.et al., “III-V nanowires – extending a narrowing road,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2047–2060 (2010)
[53] Chen, L., Fung, W.Y., Lu, W., “Vertical nanowire heterojunction devices based on a clean Si/Ge interface,” Nano Letters, vol. 13, no. 11, pp. 5521–5527 (2013)
[54] Wen, C.Y.et al., “Fabrication and properties of abrupt Si-Ge heterojunction nanowire structures,” Electrochemical Society Transactions, vol. 33, no. 6, pp. 671–680 (2010)
[55] Björk, M.T.et al., “One-dimensional heterostructures in semiconductor nanowhiskers,” Applied Physics Letters, vol. 80, no. 6, pp. 1058–1060 (2002)
[56] Moselund, K.E.et al., “InAs–Si nanowire heterojunction tunnel FETs,” IEEE Electron Device Letters, vol. 33, no. 10, pp. 1453–1455 (2012)
[57] Shik, A.et al., “Electrical properties and band diagram of InSb-InAs nanowire type-III heterojunctions,” Journal of Applied Physics, vol. 113, pp. 104307.1–8 (2013)
[58] Dey, A.W., et al., “Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors,” Nano Letters, vol. 13, no. 12, pp. 5919−5924 (2013)
[59] Tomioka, K., Fukui, T., “Recent progress in integration of III–V nanowire transistors on Si substrate by selective-area growth,” Journal of Physics D: Applied Physics, vol. 47, no. 39, pp. 394001.1–12 (2014)
[60] Lauhon, L.J.et al., “Epitaxial core-shell and core multishell nanowire heterostructures,” Nature, vol. 420, pp. 57–61 (2002)
[61] Greytak, A.B.et al., “Growth and transport properties of complementary germanium nanowire field-effect transistors,” Applied Physics Letters, vol. 84, no. 21, pp. 4176–4178 (2004)
[62] Lu, W.et al., “One-dimensional hole gas in germanium silicon nanowire heterostructures,” Proceedings of the National Academy of Sciences of the United States of America (PNAS), vol. 102, no. 29, pp. 10046–10051 (2005)
[63] Xiang, J., Lu, W., Yu, Y., Wu, Y., Yan, H., Lieber, C.M., “Ge/Si nanowire heterostructures as high-performance field-effect transistors,” Nature, vol. 441, no. 25, pp. 489–493 (2006)
[64] Dayeh, S.A., Gin, A.V., Picraux, S.T., “Advanced core/multishell germanium/silicon nanowire heterostructures: morphology and transport,” Applied Physics Letters, vol. 98, no. 16, pp. 163112.1–3 (2011)
[65] Peng, X., Logan, P., “Electronic properties of strained Si/Ge core-shell nanowires,” Applied Physics Letters, vol. 96, no. 14, pp. 143119.1–3 (2010)
[66] Peng, X., Tang, F., Logan, P., “First principles study of Si/Ge core-shell nanowires – structural and electronic properties,” in Nanowires – Fundamental Research, Hashim, A. (ed.) (2011), DOI: 10.5772/16298
[67] Walle, C.G. Van de, Weber, J.R., Janotti, A., “Role of hydrogen at germanium/dielectric interfaces,” Thin Solid Films, vol. 517, pp. 144–147 (2008)
[68] Trammell, T.E.et al., “Equilibrium strain-energy analysis of coherently strained core-shell nanowires,” Journal of Crystal Growth, vol. 310, no. 12, pp. 3084–3092 (2008)
[69] Dorne, E.et al., “Hydrogen annealing of arrays of planar and vertically stacked Si nanowires,” Applied Physics Letters, vol. 91, pp. 233502.1–3 (2007)
[70] Cherns, P.D.et al., “Electron tomography of gate-all-around nanowire transistors,” 16th International Conference on Microscopy of Semiconducting Materials, Journal of Physics: Conference Series, vol. 209, pp. 012046.1–4 (2010)
[71] Xiong, W.et al., “Improvement of FinFET electrical characteristics by hydrogen annealing,” IEEE Electron Device Letters, vol. 25, no. 8, pp. 541–543 (2004)
[72] Tezuka, T.et al., “Observation of mobility enhancement in strained Si and SiGe tri-gate MOSFETs with multi-nanowire channels trimmed by hydrogen thermal etching,” IEEE International SOI Conference Proceedings, pp. 139–140 (2006)
[73] Morioka, N., Suda, J., Kimoto, T., “Anisotropy in surface self-diffusion on Si nanowires and its impact on wire instability in hydrogen annealing,” Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 91–92 (2013)
[74] Liu, H.I.et al., “Self-limiting oxidation for fabricating sub-5 nm silicon nanowires,” Applied Physics Letters, vol. 64, no. 11, pp. 1383–1385 (1994)
[75] Fazzini, P.-F.et al., “Modeling stress retarded self-limiting oxidation of suspended silicon nanowires for the development of silicon nanowire-based nanodevices,” Journal of Applied Physics, vol. 110, pp. 033524.1–8 (2011)
[76] Kao, D.-B.et al., “Two-dimensional thermal oxidation of silicon – II. Modeling stress effects in wet oxides,” IEEE Transactions on Electron Devices, vol. 35, no. 1, pp. 25–37 (1988)
[77] Büttner, C.C., Zacharias, M., “Retarded oxidation of Si nanowires,” Applied Physics Letters, vol. 89, pp. 263106(1–3) (2006)
[78] Shi, X.et al., “Review of silicon nanowire oxidation,” ECS Transactions, vol. 34, no. 1, pp. 535–540 (2011)
[79] Khalilov, U.et al., “Self-limiting oxidation in small-diameter Si nanowires,” Chemistry of Materials, vol. 24, pp. 2141−2147 (2012)
[80] Boyd, E.J., Uttamchandani, D., “Measurement of the anisotropy of Young's modulus in single-crystal silicon,” Journal of Microelectromechanical Systems, vol. 21, no. 1, pp. 243–249 (2012)
[81] Wortman, J.J., Evans, R.A., “Young's modulus, shear modulus, and Poisson's ratio in silicon and germanium,” Journal of Applied Physics, vol. 36, no. 1, pp. 153–156 (1965)
[82] Zhu, Y.et al., “Mechanical properties of vapor-liquid-solid synthesized silicon nanowires,” Nano Letters, vol. 9, no. 11, pp. 3934–3939 (2009)
[83] Han, X.et al., “Low-temperature in situ large-strain plasticity of silicon nanowires,” Advanced Materials, vol. 19, no. 16, pp. 2112–2118 (2007)
[84] Cea, S.M.et al., “Process modeling for advanced device technologies,” Journal of Computational Electronics, vol. 13, pp. 18–32 (2014)
[85] Alekseev, P.et al., “Measurement of Young's modulus of GaAs nanowires growing obliquely on a substrate,” Semiconductors, vol. 46, no. 5, pp. 641–646 (2012)
[86] Lee, B., Rudd, R.E., “First-principles study of the Young's modulus of Si <001> nanowires,” Physical Review B, vol. 75, pp. 041305(1–4) (2007)
[87] Leu, P.W., Svizhenko, A., Cho, K., “Ab initio calculations of the mechanical and electronic properties of strained Si nanowires,” Physical Review B, vol. 77, pp. 235305(1–14) (2008)
[88] Petersen, K.E., “Silicon as a mechanical material,” Proceedings of the IEEE, vol. 70, no. 5, pp. 420–456 (1982)
[89] Ando, T.et al., “Effect of crystal orientation on fracture strength and fracture toughness of single crystal silicon,” Proceedings 17th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), pp. 177–180 (2004)
[90] Kang, K., Cai, W., “Size and temperature effects on the fracture mechanisms of silicon nanowires: molecular dynamics simulations,” International Journal of Plasticity, vol. 26, pp. 1387–1401 (2010)
[91] Sadeghian, H.et al., “On the size-dependent elasticity of silicon nanocantilevers: impact of defects,” Journal of Physics D: Applied Physics, vol. 44, pp. 072001.1–6 (2011)
[92] Schlötterer, H., “Mechanical and electrical properties of epitaxial silicon films on spinel,” Solid-State Electronics, vol. 11, no. 10, pp. 947–956 (1968)
[93] Sato, T.et al., “CMOS/SOS VLSI Technology,” in Comparison of Thin-film Transistor and SOI Technologies, Lam, H.W., Thompson, M.J. (eds.), Materials Research Society Symposium Proceedings, vol. 33, pp. 25–34 (1984)
[94] Chu, M.et al., “Strain: a solution for higher carrier mobility in nanoscale MOSFETs,” Annual Review of Materials Research, vol. 39, pp. 203–229 (2009)
[95] Rim, K., Grill, A., Wong, H.S.P, “Strained Si NMOSFETs for high performance CMOS technology,” Symposium on VLSI Technology Digest of Technical Papers, pp. 59–60 (2001)
[96] Hoyt, J.L.et al., “Strained silicon MOSFET technology,” Technical Digest of the IEEE International Electron Device Meeting (IEDM), pp. 23–26 (2002)
[97] Thompson, S.E.et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices, vol. 51, no. 11, pp. 1790–1797 (2004)
[98] Chan, V.et al., “Strain for CMOS performance improvement,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 667–674 (2005)
[99] Andrieu, F.et al., “Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node,” Microelectronic Engineering, vol. 84, no. 9–10, pp. 2047–2053 (2007)
[100] Fischetti, M.V., Laux, S.E., “Band structure, deformation potentials, and carrier mobility in strained-Si, Ge, and SiGe alloys,” Journal of Applied Physics, vol. 80, pp. 2234–2252 (1996)
[101] Fischetti, M.V., Gámiz, F., Hänsch, W., “On the enhanced electron mobility in strained-silicon inversion layers,” Journal of Applied Physics, vol. 92, pp. 7320–7324 (2002)
[102] Niquet, Y.M., Delerue, C., Krzeminski, C., “Effects of strain on the carrier mobility in silicon nanowires,” Nano Letters, vol. 12, pp. 3545–3550 (2012)
[103] Niquet, Y.M., Delerue, C., “Carrier mobility in strained Ge nanowires,” Journal of Applied Physics, vol. 112, pp. 084301.1–4 (2012)
[104] Cassé, M.et al., “Strain-Enhanced Performance of Si-Nanowire FETs,” Electrochemical Society Transactions, vol. 53, no. 3, pp. 125–136 (2013)
[105] Raskin, J.P.et al., “Mobility improvement in nanowire junctionless transistors by uniaxial strain,” Applied Physics Letters, vol. 97, pp. 042114.1–3 (2010)
[106] Persson, M.P.et al., “Charged impurity scattering and mobility in gated silicon nanowires,” Physical Review B, vol. 82, pp. 115318.1–8 (2010)
[107] Niquet, Y.M., Mera, H., Delerue, C., “Impurity-limited mobility and variability in gate-all-around silicon nanowires,” Applied Physics Letters, vol. 100, pp. 153119.1–4 (2012)