Starting from the 90 nm technology node, several semiconductor companies have introduced strain as an important booster for the performance of MOS transistors; among them we can mention IBM [1], Intel [2], Texas Instruments [3], and Freescale [4]. This consideration explains the decision to devote an entire chapter of the book to transport in strained MOS devices.

Strain affects the characteristics of MOS transistors in several respects. In fact, besides its impact on carrier transport in the device channel, strain induces shifts of the band edges affecting the threshold voltage of the transistors [5], the leakage of the source and drain junctions [6], the energy barrier to the gate dielectric and consequently the gate leakage current [7], and also the transistor reliability [8]. The present chapter, however, is essentially focused on the methodologies and the models necessary to account for the strain effects on transport in MOS transistors, more precisely on the low field mobility and the drain current IDS.

The chapter is organized as follows. After a concise introduction to the fabrication techniques used for strain engineering in Section 9.1, all the relevant definitions related to stress and strain in cubic crystals are described in Section 9.2. Correct evaluation of the strain tensor in the crystal coordinate system is the first step necessary to model the effects of strain on the band structure of n-type and p-type MOS transistors, which are described respectively in Section 9.3 and 9.4.