THE SHARED MEMORY MODEL

A model is a theoretical or physical object whose analysis or observation allows for exploration of another real object or process. A model represents an explored object in a simplified manner by taking into account only its basic features. Due to simplifications models are easier to analyze than the corresponding real objects.

The subject of our interest are models of computers enabling the study of computational processes executed within those computers. The models, called models of computation, are helpful when analyzing and designing algorithms, as well as in determining performance metrics used for evaluation of algorithms (see Section 3.1). Models of computation should not be associated with a specific computer architecture, or with a class of such architectures. In other words, their independence from hardware is essential. Another essential feature should be versatility that ensures that algorithms developed adopting these models can be implemented and run on computers with different architectures. It is particularly important in the field of parallel computing where diversity of architectures is high. As a result of this diversity several models have been advanced. Unfortunately, due to relatively large number of requirements that a model should satisfy, partly in conflict with each other, none of the models developed so far has become a generally accepted model of parallel computation. The frequently used are the shared memory model (or parallel random access machine model, PRAM) and the network model. They correspond to parallel computation conducted with the use of shared memory and by sending messages over some communication network. Before discussing these models, we will present a sequential model of computation underlying the PRAM model.

2.1.1 The RAM model

A widely accepted model of sequential computation is the machine with random access memory (RAM). The model consists of a processor and memory containing a potentially infinite number of cells Mi for i = 1, 2, 3, … (Figure 2.1). In each memory cell identified by its address i, a finite value expressed in binary, perhaps very large, can be stored. The model assumes that the time to read (write) a value from (in) a cell Mi is constant and equal to unit time, regardless of a cell address.