Skip to main content Accessibility help
×
Hostname: page-component-8448b6f56d-c4f8m Total loading time: 0 Render date: 2024-04-24T07:59:59.526Z Has data issue: false hasContentIssue false

2 - High-speed digital design

Published online by Cambridge University Press:  14 September 2009

Razak Hossain
Affiliation:
STMicroelectronics, San Diego
Get access

Summary

Microprocessors since 1989

In 1989 a forward-looking paper attempted to determine the characteristics of microprocessors in the year 2000. Called “Microprocessors circa 2000”, the paper hypothesized that a high-performance microprocessor in the year 2000 would have an area of 1 square inch (645 sq mm), contain 50 million transistors, and run at above 250 MHz [1]. The overall performance of the microprocessor was estimated at 2000 million instructions per second (MIPS), achieved by the employment of two or three cores, each with a performance of 750 MIPS. Forward-looking papers often have somewhat fanciful conceits of future developments, illustrating the witticism that predictions tend to be difficult if they involve the future. This prediction, however, was based on many years of microprocessor development, leading to a broadly accurate prediction of things to come. The International Solid State Circuit Conference (ISSCC), held in early 2000, presented a number of microprocessors whose transistor counts and area were within 2× of the prediction. Since much of the area of a microprocessor is composed of on-chip memory, the prediction for transistor count was achieved soon afterwards. The prediction of 2000 MIPS for the maximum performance of the system also proved to be accurate. The interesting discrepancy was in the way that the performance of the microprocessor was achieved. Instead of employing a number of processors operating at 250 MHz, most high end microprocessors were single core designs running at or above 1 GHz.

Type
Chapter
Information
High Performance ASIC Design
Using Synthesizable Domino Logic in an ASIC Flow
, pp. 18 - 36
Publisher: Cambridge University Press
Print publication year: 2008

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

Gelsinger, P. P.et al., Microprocessors circa 2000, IEEE Spectrum, October 1989.Google Scholar
R. H. Dennard et al., Ion implanted MOSFET's with very short channel lengths, IEEE International Electron Devices Meeting, 1973.
Harris, D., Skew-Tolerant Circuit Design, Morgan Kaufmann Publishers, San Francisco, CA, 2001.Google Scholar
Hrishikesh, M. S.et al., The optimal depth per pipeline stage is 6 to 8 fan-out of four inverter delays, 29th Annual International Symposium on Computer Architecture, 2002.Google Scholar
Chinnery, D. and Keutzer, K., Closing the Gap Between application-specific integrated circuit and Custom: Tools and Techniques for High Performance application-specific integrated circuit Design, Kluwer Academic Publishers, Norwell, MA, 2002.Google Scholar
Hennessy, J. L. and Paterson, D. A., Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, San Francisco, CA, Second Edition, 1996.Google Scholar
Kogge, P. M. and Stone, H. S., A parallel algorithm for the efficient solution of a general class of recurrence equations, IEEE Transactions on Computers 22(8), August 1973.Google Scholar
R. Hossain and L. B. Huang, System and method for predictive comparator following addition, US Patent Number 6820109 B2, November 2004.
Hossain, R., Herbert, J., Gouger, J. F. and Bechade, R., A 5.2 ns cycle time floating point unit macrocell, 24th European Solid-State Circuits Conference, The Hague, Netherlands, 1998.Google Scholar
J. C. Herbert. R. Hossain and R. A. Bechade, Floating point unit having a unified adder–shifter design, US Patent Number 6148315, April 1998.
Markovic, D.et al., Methods for true energy performance optimization, IEEE Journal of Solid State Circuits 39(8), August 2004.CrossRefGoogle Scholar
Johnson, M., Superscalar Microprocessor Design, Prentice-Hall, Englewood Cliffs, NJ, 1991.Google Scholar

Save book to Kindle

To save this book to your Kindle, first ensure coreplatform@cambridge.org is added to your Approved Personal Document E-mail List under your Personal Document Settings on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part of your Kindle email address below. Find out more about saving to your Kindle.

Note you can select to save to either the @free.kindle.com or @kindle.com variations. ‘@free.kindle.com’ emails are free but can only be saved to your device when it is connected to wi-fi. ‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.

Find out more about the Kindle Personal Document Service.

Available formats
×

Save book to Dropbox

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Dropbox.

Available formats
×

Save book to Google Drive

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Google Drive.

Available formats
×