Timing diagrams, which electrical engineers have been using for years, are a new addition to the UML. They depict the change in state or condition of a classifier instance or role over time, often in response to external events. Timing diagrams are often used in the design of embedded software, such as control software for a fuel injection system in an automobile, although they occasionally have their uses for business software too. A UML timing diagram should be created when timing, not sequence, is of critical importance.

General Guidelines

Figure 57 depicts a typical UML timing diagram, showing how a project team progresses through the various high-level stages of a project's life cycle. In this case the team shifts back and forth between four discrete activities/states—Implement, Deploy, Support, and Wait. Several time observations are marked using the format “t=XXXX,” where XXXX is an event or actual time value. A time constraint, {t==0 . .4 weeks}, indicates the potential length of time that the initial implementation efforts may take.

It is interesting to note that Figure 57 could actually be considered a value stream map (Poppendieck and Poppendieck 2003) because it indicates the amount of time that the team spends adding value (working in the first three states) in comparison to the time wasted waiting.

Draw a Continuous Timing Diagram for Analog Values

Figure 58 shows how you would model a continuous stream of analog values, in this case the changing percentage over time of decided voters in an election.