It is possible to achieve higher performance with pipelined templates by applying timing assumptions rather than designing them to be quasi-delay-insensitive. In fact, designing templates with assumptions on the relative order of certain signal transitions can not only speed up the operation of the circuit but also lower area and power consumption.

Williams' PS0 pipeline

Figure 12.1 shows one stage of Williams' PS0 pipeline, one of the earliest proposed timed pipeline templates. The pipeline stage consists of a dual-rail function block F and a completion detector. The output of the completion detector is fed back to the previous stage as the acknowledge signal. The completion detector checks the validity or absence of data at the outputs. There is no input-completion detector.

The function block is implemented using domino logic. The precharge and evaluation control input Pc of each stage comes from the output of the next stage's completion detector. The precharge logic can hold its data outputs even when its inputs are reset, therefore it also provides the functionality of an implicit latch. Each completion detector verifies the completion of every computation and precharge of its associated function block.

The operation of the PS0 pipeline is quite simple. Stage N is precharged when stage N + 1 finishes evaluation. Stage N evaluates when stage N + 1 finishes reset. This protocol ensures that consecutive data tokens are always separated by bubbles also known as holes.