As mentioned in Chapter 7, in delay-insensitive (DI) design it is assumed that the delays of the composite gates and wires can be unbounded and thus the circuits will work correctly for any arbitrary set of time-varying gate and wire delays. This is the most conservative and robust delay model, but it has been shown that it is not very practical because very few DI circuits exist. Therefore the notion of quasi-delay-insensitive (QDI) circuits has been developed. These circuits work correctly regardless of the values of the delays in the gates and wires, except for those associated with wire forks designated isochronic. By definition, the difference in the times at which a signal arrives at the ends of an isochronic fork is assumed to be less than the minimum gate delay. If these isochronic forks are guaranteed to be physically localized to a small region, this assumption can be easily met and the circuits can be practically as robust as DI circuits. This chapter covers a variety of QDI templates designed with pipelined handshaking. Note, however, that the QDI model is also used in circuits that implement enclosed handshaking (see Chapter 8) and has been extended to include the assumption of isochronic propagation through a number of logic gates.

Weak-conditioned half buffer

The first QDI template we will cover is the weak-conditioned half buffer (WCHB).