Introduction

In its simplest form [1], a sample and hold circuit has the circuit shape shown in Fig. 3.1. The signal input arrives through a 50 Ω co-axial line, to find a 50 Ω termination, and is then sampled periodically by means of the sampling gate. This gate is shown as a simple switch in Fig. 3.1.

The switch closes for a very short time, τ, short enough for it to be assumed that any change in the input signal over that time may be neglected. During this short time, the sampling capacitor, cs, will begin to charge up towards the value that the input signal has at the instant of sampling. The time constant, Tin, associated with this charging process will be 25 Cs, because Cs will see a source impedance of 25 Ω when the switch is closed: the 50 Ω resistor in parallel with the 50 Ω input line.

When the switch is open, Cs is left providing an input to the voltage follower, A in Fig. 3.1. The output from the circuit is thus ‘held’ in between samples, provided the voltage follower can be made to have a high enough input impedance.

How the circuit actually behaves is mainly determined by the relative values of the input time constant, Tin, and the sampling time, τ. Three cases will be considered in the following three sections: Tin ≫ τ, Tin ≪ τ, and the particularly interesting case where Cs is replaced by an open circuited length of transmission line.