As computer chip technologies evolve from aluminum-based metallization schemes to their copper-based counterparts, Electrochemical Deposition (ECD) is emerging as a viable deposition technique for copper (Cu) interconnects. This paper presents the results of a first-pass study to examine the underlying mechanisms that control ECD Cu nucleation, growth kinetics, and post-deposition microstructure evolution (self-annealing), leading to the development and optimization of an ECD Cu process recipe for sub-quarter-micron device generations. The influence of bath composition, current waveform, type and texture of Cu seed layer, and device feature size (scaling effect) on the evolution of film texture, morphology, electrical properties, and fill characteristics was investigated using a manufacturing-worthy ReynoldsTech 8” wafer plating tool. Resulting films were analyzed by X-ray Diffraction (XRD), four-point resistivity probe, Focused-Ion-Beam Scanning Electron Microscopy (FIB-SEM), and Atomic Force Microscopy (AFM). These investigations identified an optimized process window for the complete fill of aggressive device structures with pure Cu with resistivity ∼ 2.0 µΩ-cm and smooth surface morphology.