The combined effects of isolation stress, active area size, and SiGe misfit strain on dislocation generation in an advanced SiGe heterojunction bipolar transistor (HBT) process were studied. Eight-inch wafers were patterned with polysilicon-filled deep, and oxide-filled shallow trench isolation similar to that used in IBM's analog SiGe HBT technology. Half of the wafers were subjected to an additional stress-producing oxidation prior to SiGe growth. Si1−xGex films containing 0, 5.5, 9, and 13 at.% Ge were grown epitaxially by ultrahigh vacuum chemical vapor deposition (UHV CVD). The films were of constant thickness with an intrinsic Si cap. Some samples received an additional relaxation anneal following deposition. After the growth and anneal cycles, the dislocation density was determined by transmission electron microscopy (TEM). On nonstressed samples, no dislocations were observed in the device areas, even at Ge concentrations which are not stable to misfit dislocation generation in blanket form. This small area effect has been observed on patterned substrates that do not have functional device isolation. On the stressed-isolation wafers, the compressive stress from the oxidation of the trench sidewalls was found to intensify stress in the SiGe films, and to lower the critical strain at which misfit dislocations appeared. In large active areas on these wafers, two distinct dislocation regions were observed. Defects at the edge resembled those caused by isolation stress, while the defects in the center were more typical of the misfit dislocations associated with lattice-mismatch epitaxial films. It is clear that isolation stress must be minimized when fabricating integrated circuits using SiGe epitaxial films. It is also evident that SiGe films grown on nonstressed isolation exhibit the same increase in critical thickness with decreasing lateral dimension that has been observed on much simpler patterned substrates.