In this study, the effect of the addition of electrolytes in a given ionic strength to various high-purity silica suspensions was investigated by measurement of the removal rates (RR's) in CMP processes on oxide layers under the same experimental conditions. As so-called slurries the following suspensions were used: i) silica sols produced by the Stöber process, ii) conventional silica sols based on alkali silicate as well as iii) suspensions of fumed silica, with the same SiO2 concentration in each suspension. Ionic strength of the added electrolyte was adjusted to e.g. 0.065 mol/l, with the electrolytes being HCl, NH4Cl, KOH, or binary mixtures of these substances.

These investigations revealed significant differences of the polishing behaviour between the different types of silica dispersions as slurries. While for the Stöber sols investigated, the RR's are highest in the acidic range and almost negligible in the alkaline pH range, fumed silica suspensions show an entirely different behaviour: RR is very low for acidic pH-values, and increases with the alkalinity of the slurry. In contrast to these observations, the RR's of slurries based on conventional silica sols are highest around the neutral point, and show a decrease for both more alkaline and acidic pH-values. In comparison to the other two types of material, these suspensions have a high amount of electrolyte background, originating from their manufacturing process.

A model is developed to explain these results in a comprehensive manner. It involves effects of the electrolyte type and the ionic strengths as well as influences of the particle size.

In situ investigations of the chemical and mechanical mechanisms during CMP processes require analytical access to the wafer surface while interacting with the slurry and the pad under polishing conditions. In this study me make use of novel, specifically prepared, and self-designed Si wafer called microstructured single reflection elements (mSRE) utilizing the IR transparency of silicon [1]. The mSRE's enable in and ex situ attenuated total reflection (ATR) Fourier transform infrared (FTIR) investigations at the interface between silicon and the ambient with an enhanced usable spectral range. So, a thin silicon oxide layer or the polishing slurry can be investigated in the entire mid and far infrared spectral region. These mSRE wafers were placed at a simple reflection accessory of a FTIR spectrometer and either wet etched by a buffered oxide etch or polished using a CMP equivalent polishing configuration. During CMP the change of typical vibration bands of SiO2 layers and slurry constituents are observed. It was shown that the sensitivity as well as the surface selectivity of the experimental setup enables slurry and thin-film characterisations within the thickness range of monolayers. Surprisingly, the spectral features of the pad have not been observed during the polishing investigations.

Silicon germanium (SiGe) is considered to substitute silicon (Si) as channel material of p-type MOSFET in future CMOS generations due to its higher hole mobility. In this work we investigate SiGe channels with a germanium concentration of 23 at% and 30 at%, even though the mobility is expected to be higher with even more germanium in the alloy. Low pressure chemical vapor deposition was used for SiGe deposition. A state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50 nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, hafnium-based dielectric and titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was determined using the charge pumping technique. The device characteristics of n- and p-MOSFETs with SiGe channels are compared to conventional Si channel devices. Short channel mobility was extracted with the gM,LIN-Method.

Ta based films are important building blocks for modern microelectronic applications. To meet the requirements of miniaturization, atomic layer deposition appears to be an alternative technology in comparison to PVD and CVD. In the present paper investigations of a thermal TBTDET ALD process will be presented with emphasis to the first ALD reaction cycles on native silicon oxide and HF etched silicon surfaces. The investigations show that the substrate chemistry is a crucial parameter for the film growth and appears to be a key to control the ALD deposition. The investigations were done by XPS without any vacuum break between the deposition and the surface analysis.

Deposition steps in CVD and ALD applications usually not only cover the surface of the substrate surface but also the walls of the chamber inside. Regular removal of those residuals has to be done to obtain stable and repeatable deposition results with uniform surfaces at acceptable particle levels. The high requirements to sustain stable processes has lead to more frequent chamber cleans. NF3 has emerged as the main clean gas for remote clean applications. While it meets the above mentioned requirements and is considered to fit easily into the fab gas supply it is relatively expensive. The work presented here investigates argon/nitrogen diluted fluorine (F2) as an alternative clean gas with a significantly reduced environmentally destructive global warming emission (GWP). The cleaning behaviour with respect to different materials (SiON, TaN, TiN, W, SiO2) was studied. It is found that in general argon/nitrogen diluted fluorine achieves etch rates comparable to those obtained by NF3 when the comparison is based on the amount of fluorine transported into the reactor.

The major aim of CMP is not the removal of excess material but the planarization of the surface. Therefore the determination of the planarization length appears to be more important than the removal rate itself. It has been shown, that the planarization length is not a constant process parameter, but is related to the removal respectively to the polish time in a square root behaviour. Founded on models proposed by Boning, Ouma, et. al. we applied a sequential polish on a single quasi infinite step. The resulting profile could be simulated by a sequential convolution of the surface contour with a Gaussian transfer function.

To come closer to the situation on a chip pattern we investigated the planarization behaviour on a specific pattern of the MIT854AZ copper CMP test chip, where a large area of unpatterned surface touches a pattern with a specific constant density.

The 200 mm wafer samples consisted of RIE structured oxide films covered with 850 nm ECD copper. The polish was performed on a standard semiconductor manufacturing tool, using a commercial consumables set. The surface profiles were determined by a high resolution profiler within the polishing sequence. The densely patterned areas are removed within a certain polishing time while the transition point between the unpatterned and patterned area appears as a global step. The deposited copper thickness is sufficient to study the contour evolution in both phases, before and after removal of the dense pattern. The paper presents the experimental results on the contour evolution for the patterned fields as well as the global step.

The IGAM engineering company for applied mechanics Ltd. developed an active piezocontrolled carrier for CMP. It uses several, by means of piezo-stacks individually controllable rings. The carrier is optimized regarding its stiffness and reliability by means of threedimensional finite element calculations. The high stiffness and positioning accuracy of the system allows the exact control of different surface profiles and thus the purposeful attitude of the pressure and removal profile independently of the polishing pressure. Tests show a very homogeneous pressure and removal distribution in the circumference of the wafer. The concept is transferable on further wafer diameters, whereby the width of the individual zones can be widely adapted to the requirements of the desired removal profile. Results of finite element analysis for a 12” prototype are available. The variable concept allows to upgrade existing CMP machines. The aims of current developments are the integration of in-situ-pressure determination to control the process, wireless transfer of energy and data to the carrier and the control of the local removal profile.

In spite of the fact, that the main purpose of CMP is the planarization of surfaces, most processes are optimized with respect to the removal rate. This might be due to a lack in techniques for the determination of the planarization behavior. The commonly used expression “Planarization Length” implies a maximum lateral extension over which the planarization is obtained and which can not be improved. Several attempts have been made to determine the planarization length by studying the CMP on different test patterns. The general problem in the interpretation of the data is the interaction of neighboring pattern with different pattern densities. This problem does not apply to the most simple pattern possible, which is a single step with an extension of the up and down areas much larger than the planarization length. In this case the spatial derivative of the resulting contour after CMP is directly the demanding transfer function to be used for the convolution. This concept, initially proposed by Boning et. al., was applied to evaluate the polish of copper and silicon oxide. Wafers with concentrically steps in Cu or SiO2 films with an extension of 1 to 5 cm have been prepared. During polish, the initially infinite steep step widens up, yielding the planarization length as a function of the removal respective the polishing time. Significant differences in the evaluation of the planarization length could be quantified depending on the pad, slurry and tool parameters. Our first experiments revealed a decrease in planarization length by the addition of BTA in a copper slurry. We believe that the SPR method enables a unambiguous, pattern independent determination of the planarization capability in CMP.