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The collective response of electrons in an ultrathin foil target irradiated by an ultraintense (
) laser pulse is investigated experimentally and via 3D particle-in-cell simulations. It is shown that if the target is sufficiently thin that the laser induces significant radiation pressure, but not thin enough to become relativistically transparent to the laser light, the resulting relativistic electron beam is elliptical, with the major axis of the ellipse directed along the laser polarization axis. When the target thickness is decreased such that it becomes relativistically transparent early in the interaction with the laser pulse, diffraction of the transmitted laser light occurs through a so called ‘relativistic plasma aperture’, inducing structure in the spatial-intensity profile of the beam of energetic electrons. It is shown that the electron beam profile can be modified by variation of the target thickness and degree of ellipticity in the laser polarization.
Despite improvements in outcomes after completion of the Fontan circulation, long-term functional state varies. We sought to identify pre- and postoperative characteristics associated with overall function.
Methods and Results
We analyzed data from 476 survivors with the Fontan circulation enrolled in the Pediatric Heart Network Fontan Cross-sectional Study. Mean age at creation of the Fontan circulation was 3.4 plus or minus 2.1 years, with a range from 0.7 to 17.5 years, and time since completion was 8.7 plus or minus 3.4 years, the range being from 1.1 to 17.3 years. We calculated a functional score for the survivors by averaging the percentile ranks of ventricular ejection fraction, maximal consumption of oxygen, the physical summary score for the Child Health Questionnaire, and a function of brain natriuretic peptide. The mean calculated score was 49.5 plus or minus 17.3, with a range from 3 to 87. After adjustment for time since completion of the circulation, we found that a lower score, and hence worse functional state, was associated with: right ventricular morphology (p less than 0.001), higher ventricular end-diastolic pressure (p equals 0.003) and lower saturations of oxygen (p equals 0.047) prior to completion of the Fontan circulation, lower income for the caregiver (p equals 0.003), and, in subjects without a prior superior cavopulmonary anastomosis, arrhythmias after completion of the circulation (p equals 0.003). The model explained almost one-fifth (18%) of the variation in the calculated scores. The score was not associated with surgical centre, sex, age, weight, fenestration, or the period of stay in hospital after completion of the Fontan circuit. A validation model, using 71 subjects randomly excluded from initial analysis, weakly correlated (R equals 0.17, p equals 0.16) with the score calculated from the dataset.
Right ventricular morphology, higher ventricular end-diastolic pressure and lower saturations of oxygen prior to completion of the Fontan circuit, lower income for the provider of care, and arrhythmias after creation of the circuit, are all associated with a worse functional state. Unmeasured factors also influence outcomes.
More than 15 years—nine election cycles—have passed since a comprehensive set of state legislative election data was compiled and made available to researchers and practitioners: the Inter-University Consortium for Political and Social Research's (ICPSR) State Legislative Election Returns in the United States dataset (Study #8907) collected by Malcolm Jewell (Jewell 1991) and containing observations from 1967 to 1988. With this hiatus in mind, we set out at various times initially—in three independent efforts (Berry and Carsey; Niemi, and Powell; Snyder)—to gather legislative election data for all states and elections since 1988. In addition, Berry and Carsey (2005) cleaned the original dataset to make it more accurate and usable; their corrections led to the release of a revised ICPSR dataset (Study #3938). The culmination of these efforts is a dataset containing information about general elections for state legislative seats from 1967 to 2003, now available through ICPSR (Study 21480).
The present essay briefly examines evidence for the development of the mendicant orders, focusing on their relationship to important members of the middle and upper classes in the communes as one of the chief ways in which they gained popularity and public support. These orders came into existence between the late twelfth century and the latter half of the thirteenth. Their increased involvement with the laity was both a direct product of their concern with the needs of the contemporary church and a source of conflict between them and the existing monastic and diocesan clergy. The experience of the Humiliati in various dioceses in northern Italy illustrates an important point, namely the growing divisions within the church and the tendency to label various groups as heretical. The condemnation of the Humiliati and other groups by Pope Lucius III in Verona in 1183 is a sign of the increasing sensitivity to the danger of heresy among the laity within the leadership of the church.
Three dimensional models of single chip SiC power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, and heat transfer coefficients on temperature and thermal stress contours. Silicon nitride, aluminum-nitride, alumina were compared as substrates with or without an additional layer of CVD diamond on either top or bottom of the surfaces. Simulated heat fluxes of 100 to 300 watts/cm2 resulted in device junction temperatures in the range of 377 to 535 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 3350 watts/m2 K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 535 K. Both the maximum and minimum chip temperature decreased with increasing heat transfer coefficient from 50 to 5000 watts/m2 K. In the applied heat flux range, the minimum and maximum Von Mises stress of a simulated single SiC device sub-module was between 946 MPa to 1.31GPa. If consistent with simulation results, CVD diamond integrated substrates should be superior to those comprised of only AlN, Al2O3, and Si3N4. Experimental validation of ANSYS results and more extensive multiple-chip power module simulations will also be explored.
A systematic study is presented of the heteroepitaxial growth of B12As2 on m-plane 15R-SiC. In contrast to previous studies of B12As2 on other substrates, including (100) Si, (110) Si, (111) Si and (0001) 6H-SiC, single crystalline and untwinned B12As2 was achieved on m-plane 15R-SiC. Observations of IBA on m-plane (1100)15R-SiC by synchrotron white beam x-ray topography (SWBXT) and high resolution transmission electron microscopy (HRTEM) confirm the good quality of the films on the 15R-SiC substrates. The growth mechanism of IBA on m-plane 15R-SiC is discussed. This work demonstrates that m-plane 15R-SiC is potentially a good substrate choice to grow high quality B12As2 epilayers.
The commercialization of 4H-SiC MOSFETs will greatly depend on the reliability of gate oxide. Long-term gate oxide reliability and device stability of 1200 V 4H-SiC MOSFETs are being studied, both under the on- and off-states. Device reliability is studied by stressing the device under three conditions: (a) Gate stress - a constant gate voltage of +15 V is applied to the gate at a temperature of 175°C. The forward I-V characteristics and threshold voltage are monitored for device stability, (b) Forward current stress – devices are stressed under a constant drain current of Id = 4 A and Vg = 20 V. The devices were allowed to self-heat to a temperature of Tsink = 125°C and the I-V curves are monitored with time, and (c) High temperature reverse bias testing at 1200 V and 175°C to study the reliability of the devices in the off-state. Our very first measurements on (a) and (b) show very little variation between the pre-stress and post-stress I-V characteristics and threshold voltage up to 1000 hrs of operation at 175°C indicating excellent stability of the MOSFETs in the on-state. In addition, high temperature reverse bias stress test looks very promising with the devices showing very little variation in the reverse leakage current with time.
We have observed a gate-bias stress induced instability in both the threshold voltage of SiC MOSFETs and the flatband voltage of SiC MOS capacitors. The magnitude of this bias stress-induced instability generally increases linearly with log time, with no saturation of the effect observed, even out to 100,000 seconds. The magnitude also increases with increasing gate field. A positive gate-bias stress causes a positive shift and a negative gate-bias stress causes a negative shift, consistent with electron tunneling into or out of oxide traps near the SiC / SiO2 interface as opposed to mobile ions drifting across the gate oxide. The effect is repeatable.
Fabrication and characteristics of high voltage, normally-on JFETs in 4H-SiC are presented. The devices were built on 5x1015 cm-3 doped, 12 μm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 10 m Ω-cm2 and a blocking voltage of 1.8 kV were measured. Device characteristics were measured for temperatures up to 300oC. An increase of specific on-resistance by a factor of 5 and a decrease in transconductance were observed at 300oC, when compared to the value at room temperature. This is due to a decrease in bulk electron mobility at elevated temperature. A slight negative shift in pinch-off voltage was also observed at 300oC. The devices demonstrated robust DC characteristics for temperatures up to 300oC, and stable high temperature inverter operation in a power DC-DC converter application, using these devices, is reported in this paper.
Improved AlNi-based ohmic contacts to p-type 4H-SiC have been achieved using low energy ion (Al+) implantation, the addition of a thin Ti layer, and a novel two-step implant activation anneal process. Resistivities sometimes as low as 5×10−5 Ω-cm2 were reached by doping the surface region of lightly p-doped 4H-SiC epilayers via low energy Al+ implantation. Acceptor activation was achieved by annealing the samples with a 1400+1700°C two-step sequence in an Ar atmosphere, which also yielded improved surface morphology when implanted samples were capped with photo resist during the anneals. In this study, Ti/AlNi/W contacts on implanted layers were compared to Ti/AlNi/Au contacts. Even though the resistivities are higher than those of the Ti/AlNi/W system, the reduced anneal temperature, 650°C for Ti/AlNi/Au compared to 950°C for Ti/AlNi/W implies that Ti/AlNi/Au is a promising stacking configuration. Furthermore, the effects of a longer 30 minute anneal time at 600 − 700°C, in atmospheric pressure Ar ambients was observed. Namely, the 2 minute annealing cycle used for the Ti/AlNi/W study resulted in higher anneal temperatures before ohmic characteristics were seen. This same anneal time was not sufficient for the Ti/AlNi/Au samples, whereas increasing the cycle time to 30 minutes resulted in ohmic behavior at a much lower temperature. Increasing the anneal time however, had little or no impact on reducing the required anneal temperature of the Ti/AlNi/W.
The reduction in the current gain of SiC BJTs has been observed after operating the devices for as little as 15 minutes. It is accompanied by an increase in the on-resistance of the BJT. The origin of the current gain degradation in the BJTs is investigated. Two possible mechanisms, which may be simultaneously present in the device, are thought to be responsible: (a) increase in the surface recombination particularly in the region between the emitter and the base implant, and (b) bulk recombination in the base due to the generation and growth of stacking faults. Initial observation reveals the presence of stacking fault in the base-emitter region when the device is forward-biased. At the same time, minimizing the effect of recombination from the surface using improved passivation helped in the suppression of the current gain degradation in SiC BJTs.
This paper reports our effort to develop amorphous hydrogenated silicon carbide (a-SiC:H ) films specifically designed for MEMS applications using a semiconductor-grade organosilane known as trimethylsilane (3MS) as the precursor. In our work, the a-SiC:H films were deposited in a commercial PECVD system at a fixed temperature of 350˚C using 3MS diluted in helium (He). Films with thicknesses from ~ 100 nm to ~ 2μm, a typical range for MEMS applications, were deposited. Deposition parameters such RF power, deposition pressure, and 3MS-to-He ratio were explored to obtain films with low residual compressive stresses. Low temperature, post-deposition annealing at 450˚C was used to convert the as-deposited compressive residual stresses to moderate tensile stresses, which are desired for micromachined bridges, membranes and other anchored structures. Compositional analysis indicated that films with a Si-to-C ratio of 1 could be deposited under certain conditions. Mechanical properties such as Young's modulus and fracture strength were derived from the load-deflection behavior of micromachined freestanding membranes. Nanoindentation was used to verify the Young's modulus and determine the hardness. As expected, the films exhibit insulating properties with a relative dielectric constant at 3.90 for as-deposited films and 2.69 after annealing at 1100˚C, as determined from C-V measurements. Chemical inertness was tested in aqueous, corrosive solutions such as KOH and HNA. Prototype structures were fabricated using both surface micromachining and bulk micromachining techniques to demonstrate the potential of the a-SiC:H films for MEMS applications.
Fabrication and characteristics of high voltage, high speed DMOSFETs in 4H-SiC are presented. The devices were built on 1.2×1016 cm-3 doped, 6 mm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 8.7 mW-cm2 and a blocking voltage of 950 V were measured. Device characteristics were measured for temperatures up to 300oC. An increase of specific on-resistance by 35% observed at 300oC, when compared to the value at room temperature. This is due to a negative shift in MOS threshold voltage, which decreases the MOS channel resistance at elevated temperatures. This effect cancels out the increase in drift layer resistance due to a decrease in bulk electron mobility at elevated temperature, resulting in a temperature stable on-resistance. The device operation at temperatures up to 300 oC and high speed switching results are also reported in this paper.