We report on a direct epitaxial growth approach for the heterogeneous integration of high speed III-V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBTs) structures were successfully grown on patterned Si-on-Lattice-Engineered-Substrate (SOLES) substrates using molecular beam epitaxy. DC and RF performance similar to those grown on lattice-matched InP were achieved in growth windows as small as 15×15μm2. This truly planar approach allows tight device placement with InP-HBTs to Si CMOS transistors separation as small as 2.5 μm, and the use of standard wafer level multilayer interconnects. A high speed, low power dissipation differential amplifier was designed and fabricated, demonstrating the feasibility of using this approach for high performance mixed signal circuits such as ADCs and DACs.

The advantages of fluorine co-implantation on reducing the deep P junction profile is investigated and commented as a possible valuable solution for further scaling of the NMOS transistors spacer length. On PMOS transistors, Ge+C+B cocktail junctions lead to improved short channel effects control, S/D resistance and performance over the conventional approaches. Additional laser annealing induces a partial dissolution of the doping clusters in the junction and lower the S/D transistors resistance. A performance improvement is demonstrated both for NMOS and PMOS with cocktail junctions activated by spike RTA and additional laser annealing.

Within this paper we have demonstrated the unique capability of scanning spreading resistance microscopy (SSRM) in order to evaluate and optimize the recent approaches towards the formation of advanced p-MOS devices. As shown in this paper, such an optimization requires a detailed 2D-analysis on completely processed devices as two-dimensional interactions may cause (unexpected) lateral diffusion and (de) activation of underlying profiles. Emphasis will be on junction formation using Ge- pre-amorphization and carbon based cocktail implantation coupled with activation based on solid phase epitaxial regrowth and/or millisecond laser anneal. In the case of a Ge-pre-amorphization implant followed by solid phase epitaxial regrowth, SSRM shows an obvious relationship between the presence of defects in the end of range region and halo implant de-activation. Based on the quantified 2D-profiles we can extract the lateral and vertical junction depths as well as the lateral and vertical abruptness of the extension region. A drastic reduction of the lateral diffusion for the cocktail implant versus the standard reference devices with classical spike annealing is eminent. At the same an important reduction of the lateral diffusion of the source/drain implants (HDD) under the spacer can be seen. The SSRM results also highlight the impact of different activation mechanisms on the channel implants (in particular on the shape of the halo pockets).

Several aspects of the integration of diffusion-less junctions in a NMOS and PMOS conventional flows are evaluated. Processes as Solid Phase Epitaxial Regrowth (SPER) or advanced annealing techniques, as flash or laser, demonstrates benefits not only on the 1D junction profiles but also on the transistor characteristics. An optimization of the implants and of the annealing conditions lead to improved or equivalent transistors performance and short channel effects control compared to the conventional spike RTA process. A significant gain in the overlap capacitance could allow for reduced CV/I. Furthermore the junction leakage can be lowered down to the values reached with the conventional spike RTA process.

As extensions have been up till now always used in N-MOS transistors with an activation anneal. Here, we show that also alternative doping by P can result in junction extensions that are extremely abrupt and shallow thus suitable for upcoming transistor technologies. P extensions are manufactured by amorphization, carbon co-implantation and conventional rapid thermal annealing (RTA). The impact of Si interstitials (Sii) flux suppression on the formation of P junction extensions during RTA is demonstrated. We have concluded that optimization of implants followed by RTA spike offers excellent extensions with depth Xj = 20 nm (taken at 5 × 1018 at./cm3), abruptness 3 nm/dec. and Rs = 326 Ω. Successful implementation of these junctions is straightforward for N-MOS devices with 30 nm gate length and results in an improved short channel effects with respect to the As reference.

We present B junction extensions that are extremely abrupt and shallow manufactured by amorphization, C co-implantation and conventional rapid thermal annealing (RTA). Resulting junctions have abruptnesses of 2 nm/dec better than as-implanted profiles. The most shallow B junction that has been manufactured is 15 nm deep and Rs = 626 Ω/sq. Successful implementation of these junctions is straightforward for P-MOS 30 nm gate length devices.