Interfacial dislocations (IDs) and half-loop arrays (HLAs) present in the
epilayers of 4H-SiC crystal are known to have a deleterious effect on device
performance. Synchrotron X-ray Topography studies carried out on n-type 4H-SiC
offcut wafers before and after epitaxial growth show that in many cases BPD
segments in the substrate are responsible for creating IDs and HLAs during CVD
growth. This paper reviews the behaviors of BPDs in the substrate during the
epitaxial growth in different cases: (1) screw-oriented BPD segments
intersecting the surface replicate directly through the interface during the
epitaxial growth and take part in stress relaxation process by creating IDs and
HLAs (Matthews-Blakeslee model [1] ); (2) non-screw oriented BPD half loop
intersecting the surface glides towards and replicates through the interface,
while the intersection points convert to threading edge dislocations (TEDs) and
pin the half loop, leaving straight screw segments in the epilayer and then
create IDs and HLAs; (3) edge oriented short BPD segments well below the surface
get dragged towards the interface during epitaxial growth, leaving two long
screw segments in their wake, some of which replicate through the interface and
create IDs and HLAs. The driving force for the BPDs to glide toward the
interface is thermal stress and driving force for the relaxation process to
occur is the lattice parameter difference at growth temperature which results
from the doping concentration difference between the substrate and epilayer.