We saw in Chapter 1 that technologies such as poly-Si, a-Si:H, and organic semiconductors are available for the fabrication of pixel circuits. Figure 2.1 demonstrates the three most used TFT structures. Since the bi-layer staggered bottom-gate structure requires fewer mask sets and processing steps, it is highly adopted in industrial scaled a-Si:H fabrication. However, this structure is prone to a higher leakage current, since the back-side of the a-Si:H layer is damaged during the process. An alternative solution to this structure is tri-layer structure in which an etch stopper layer is used to preserve the a-Si:H layer. However, tri-layer structure has more mask layers and process steps compared to bi-layer structure which makes the industry reluctant to adopt it. For poly-Si TFTs, the coplanar top-gate structure is the most common structure. This structure enables self-alignment, resulting in smaller design rules and TFT sizes.

Temporal and spatial non-uniformity

Each of these fabrication technologies is associated with drawbacks for circuit design. However, the key challenge in using the available technologies is the temporal or spatial non-uniformity. In a-Si:H and oxide technologies, the threshold voltage of the TFTs tends to shift (VT-shift) under prolonged bias stress condition (denoted in Figure 2.2). Considering that each pixel in most applications experiences different biasing conditions, the VT-shift will increase the non-uniformity across the panel over time. This phenomenon occurs due to charge trapping and/or defect state creation [58, 59]. The VT-shift has been modeled under different conditions including constant voltage [58, 59], constant current [60], and pulsed stress conditions [61, 62]. Depending on different applications, one of these models can be applied to extract the aging of the pixel. However, in the applications that TFT is under a constant current stress, the VT-shift is severe [60] and unlike the TFT under constant voltage stress, the VT-shift tends to increase forever.