High crystallized thin InSb epitaxial growth directly on Si substrate was investigated by molecular-beam epitaxy (MBE). Experimental results indicated that suppressing the desorption of hydrogen atoms which terminated the dangling bonds of Si wafer surface and incorporation of As around the interface between film and Si substrate were the most important to obtained high crystallized InSb film. It could be achieved by the irradiation of As4 cluster beam onto the Si wafer just before film growth. Obtained thin InSb film showed mirror like surface, and its thickness was 0.7 μm. Its electron mobility was 47,600 cm2/V-s, and FWHM of HR-XRD rocking curve was about 300 arcsec. This InSb film on Si wafer was applied to Hall element, and it passed ordinary reliability tests.

Catalytic-FGA, a combination of the standard forming gas anneal with a catalytic metal gate, has been applied to study the hydrogen passivation of III-V/Ge MOS systems. Pd (or Pt) metal gate catalytically dissociates molecular hydrogen into atomic hydrogen atoms, which then diffuse through the dielectric layer and neutralize certain semiconductor/dielectric interfacial defects. MOS systems with various interfacial qualities, including lattice-matched (n/p) In0.53Ga0.47As/10nm ALD-Al2O3 (or ZrO2)/Pd capacitors, an undoped Ge/˜1nm GeO2/4nm ALD-Al2O3/Pt capacitor, and an nGe/8nm ALD-Al2O3/Pt capacitor are fabricated to evaluate the effectiveness of C-FGA.

Silicon germanium (SiGe) is considered to substitute silicon (Si) as channel material of p-type MOSFET in future CMOS generations due to its higher hole mobility. In this work we investigate SiGe channels with a germanium concentration of 23 at% and 30 at%, even though the mobility is expected to be higher with even more germanium in the alloy. Low pressure chemical vapor deposition was used for SiGe deposition. A state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50 nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, hafnium-based dielectric and titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was determined using the charge pumping technique. The device characteristics of n- and p-MOSFETs with SiGe channels are compared to conventional Si channel devices. Short channel mobility was extracted with the gM,LIN-Method.

La-doped ZrO2 thin films were grown by O3-based atomic layer deposition on III-V (GaAs, In0.15Ga0.85As) substrates. The direct oxide deposition and the insertion of a Ge passivation layer in between the oxide and the substrate are compared in terms of the resulting density of interface traps. An improved electrical quality of the Ge-passivated interfaces concerning the energy region close to the conduction band edge in the semiconductor band-gap is demonstrated through conductance maps at various temperatures and it is attributed to Ga-related interfacial defects.

Integration of the III–V channel MISFETs on the Si platform is a potential solution to realize performance improvement and power reduction in the sub-22 nm node and beyond. To take advantage of the high electron mobility of III-Vs, the MIS interfaces of high integrity should be developed. This paper reports how the MIS characteristics vary in response to the changes in the interface composition and structures, and discusses the physics and chemistry behind these observations. We fabricated a wide variety of the high-k/III–V interface structures by employing the state-of-the-art technologies of the epitaxial wafers by MOCVD, surface reconstruction control in the MBE environment, wet/dry surface treatments optimized by utilizing XPS/AES analyses, and deposition of quality dielectrics (Al2O3, HfO2) by ALD and EB evaporation. The MIS characteristics were evaluated in the capacitor and FET structures. The talk will include the following topics: the effects of the cation composition (Al, Ga, In) of the III-V bulk on the MIS characteristics [1], the importance of the anion control (N, S) at the interface to improve the MIS characteristics, and the surface orientation ((100) vs. (111)) as a new parameter in the III-V MIS device design [1]. This work was carried out in the Nanoelectronics Project supported by NEDO/METI. [1] T. Yasuda et al., as discussed at 39th IEEE SISC (San Diego, Dec. 2008).

For the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

Channel strain in damascene gate pMOSFETs with compressive stress liner (c-SL) and embedded SiGe (eSiGe) were studied by micro-Raman spectroscopy with a quasi-line-shape UV excitation (λ=363.8nm). The channel strain profiles were obtained by the conventional mea-surement from the surface after dummy gate removal. The compressive strains at the channel edges were larger than that at the channel center for the relatively long gate length (Lgate). As the Lgate became smaller, although it became hard to recognize the strain profile, the compres-sive strain at the channel center increased by the superposition of the strain at the channel edges. However, channel strain disappeared in the measurement data for the channel length less than 160 nm. Thus, we extended the laser exposure time from 10 to 40 minutes to extract the channel strain component from obtained Raman spectra. The Raman peaks consisted of two or three peaks for the Lgate less than 160 nm. By multi peak fitting, we have succeeded in measuring the extremely large stress of - 2.4 GPa in the channel of Lgate = 30 nm pMOSFET. We also per-formed the cross-sectional measurements for the samples before and after metal-gate/high-k gate stack formation. Channel strain profiles were obtained similar to those by the conventional mea-surement. Extremely high device performance can be clearly explained by the compressive stress derived from the Raman measurements both in the Lgate dependence and eSiGe effect. We also demonstrated that Raman spectroscopy using cross-sectional measurement can evaluate the channel strain even in the MOSFETs after gate stack formation.

Zirconium tetrakis(N,N’-dimethylformamidinate), Zr-FAMD, was synthesized and evaluated as a precursor for the deposition of zirconium oxide (zirconia) thin films via Atomic Layer Deposition (ALD) technique. Zr-FAMD has a high vapor pressure and displays an exceptionally high thermal stability; it is thus well-suited to be used as a precursor for the deposition of zirconia thin films. Zr-FAMD is a more ideally-suited precursor than tetrakisethylmethylaminozirconium or TEMAZr, which has an equivalent vapor pressure, but is plagued with a rather low thermal stability, limiting its usefulness at high deposition temperatures. Zr-FAMD can be used to deposit zirconia thin films at temperatures as high as 375 °C without evidence of decomposition.

High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials. Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface. Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOX to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs. Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.

The stabilization of the tetragonal phase of 5 nm thick HfO2 films by Ge doping is investigated using x-ray absorption spectroscopy around O and Ge Kedges and by Rutherford backscattering spectrometry. We show that Ge concentrations higher than ˜5at.% are not stable during rapid thermal anneal at temperatures as low as 750°C and that the tetragonal phase of HfO2 is achieved at this Ge concentration.

We present a one-dimensional simulation study of the capacitance-voltage (C-V) and current-voltage (I-V) characteristics in MOS devices with high mobility semiconductors (Ge and III-V materials) and non-conventional gate stack with high-κ dielectrics. The C-V quantum simulation code self-consistently solves the Schrödinger and Poisson equations and the electron transport through the gate stack is computed using the non-equilibrium Green’s function formalism (NEGF). Simulated C-V characteristics are successfully confronted to experimental data for various MOS structures with different semiconductors and dielectric stacks. Simulation of I-V characteristics reveals that gate leakage current strongly depends on gate stacks and substrate materials and predicts low leakage current for future CMOS devices with high mobility materials and high-κ dielectrics.

We report on a direct epitaxial growth approach for the heterogeneous integration of high speed III-V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBTs) structures were successfully grown on patterned Si-on-Lattice-Engineered-Substrate (SOLES) substrates using molecular beam epitaxy. DC and RF performance similar to those grown on lattice-matched InP were achieved in growth windows as small as 15×15μm2. This truly planar approach allows tight device placement with InP-HBTs to Si CMOS transistors separation as small as 2.5 μm, and the use of standard wafer level multilayer interconnects. A high speed, low power dissipation differential amplifier was designed and fabricated, demonstrating the feasibility of using this approach for high performance mixed signal circuits such as ADCs and DACs.