Hostname: page-component-84b7d79bbc-7nlkj Total loading time: 0 Render date: 2024-07-26T21:22:45.686Z Has data issue: false hasContentIssue false
  • English
  • Français

Power Delivery, Signaling and Cooling for 3D Integrated Systems

Published online by Cambridge University Press:  31 January 2011

Muhannad Bakir  and
Gang Huang
Muhannad Bakir
Affiliation:
muhannad.bakir@mirc.gatech.edu, Georgia Tech, MiRC, 791 Atlantic Dr. NW, Atlanta, Georgia, 30332-0269, United States, 404-385-6276
Gang Huang
Affiliation:
gang.huang@intel.com, Intel, Austin, Texas, United States
Get access

Abstract

Three-dimensional (3D) integration of ICs provides unique opportunities to improve bandwidth, latency, and power dissipation bottlenecks of interconnects (both on- and off-chip). However, while 3D IC integration improves signal interconnection, it also presents new challenges, especially in power delivery and cooling (“thermal interconnects”). The focus of this paper is on some of the key challenges and promising technologies to address power delivery, cooling, and signaling in a 3D stack of logic ICs.

Keywords

packagingmicroelectro-mechanical (MEMS)microelectronics
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1156: Symposium D – Materials, Processes and Reliability for Advanced Interconnects for Micro-and Nanoelectronics–2009 , 2009 , 1156-D08-06-F06-06
Copyright
Copyright © Materials Research Society 2009

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] Floyd, M. S. Ghiasi, S. Keller, T. W. Rajamani, K. Rawson, F. L. Rubio, J. C. and Ware, M. S., “System power management support in the IBM POWER6 microprocessor,” IBM J. Res. & Dev., vol. 51, pp. 733–746, Nov 2007.Google Scholar
[2] Bakir, M. S. and Meindl, J. D. Integrated Interconnect Technologies for 3D Nanoelectronic Systems. Boston: Artech House, 2009.Google Scholar
[3] Sri-Jayantha, S. M., McVicker, G. Bernstein, K. and Knickerbocker, J. U. “Thermomechanical modeling of 3D electronic packages,” IBM J. Res. & Dev., vol. 52, pp. 623–634, Nov 2008.Google Scholar
[4] Shahidi, G. G. “Evolution of CMOS technology at 32 nm and beyond,” in Proc. IEEE Custom Integrated Circuits Conf., 2007, pp. 413–416.Google Scholar
[5] Emma, P. G. and Kursun, E. “Is 3D chip technology the next growth engine for performance improvement?,” IBM J. Res. & Dev., vol. 52, pp. 541–552, Nov 2008.Google Scholar
[6] Cunningham, J. E. Xuezhe, Z. Shubin, I. Ron, H. Lexau, J. Krishnamoorthy, A. V. Asghari, M., Dazeng, F. Luff, J. Hong, L. and Cheng-Chih, K., “Optical proximity communication in packaged SiPhotonics,” in IEEE Int. Conf. Group IV Photonics, 2008, pp. 383–385.Google Scholar
[7] Borkar, S. “Thousand core chips-A technology perspective,” in Proc. ACM/IEEE Design Automation Conference, 2007, pp. 746–749.Google Scholar
[8] Polka, L. Kalyanam, H. Hu, G. and Krishnamoorthy, S. “Package technology to address the memory bandwidth challenge for tera-scale computing,” Intel Technol. J., vol. 11, pp. 197–205, 2007.Google Scholar
[9] Parkhurst, J. Darringer, J. and Grundmann, B. “From single core to multi-core: preparing for a new exponential,” in IEEE/ACM Int. Conf. Computer-Aided Design, 2006, pp. 67–72.Google Scholar
[10] Joyner, J. W. Zarkesh-Ha, P., and Meindl, J. D. “Global interconnect design in a threedimensional system-on-a-chip,” IEEE Tran. Very Large Scale Integration (VLSI) Systems, vol. 12, pp. 367–372, 2004.Google Scholar
[11] Huang, G. Bakir, M. Naeemi, A. Chen, H. and Meindl, J. D. “Power delivery for 3D chip stacks: physical modeling and design implication,” in Proc. IEEE Conf. on Electrical Performance of Electronic Packaging, 2007, pp. 205–208.Google Scholar
[12] King, C. K. Sekar, D. Bakir, M. S. Dang, B. Pikarsky, J. and Meindl, J. D. “3D Stacking of Chips with Electrical and Microfluidic I/O Interconnects,” in Proc. Electronics Components and Technol. Conf., 2008.Google Scholar
[13] Sekar, D. King, C. Dang, B. Spencer, T. Thacker, H. Joseph, P. Bakir, M. S. and Meindl, J. D., “A 3D-IC Technology with Integrated Microchannel Cooling,” in Proc. Int. Interconnect Technol. Conf., 2008, pp. 13–15.Google Scholar
[14] Bakir, M. S. King, C. Sekar, D. Thacker, H. Dang, B. Huang, G. Naeemi, A. and Meindl, J. D., “3D heterogeneous integrated systems: liquid cooling, power delivery, and implementation,” in Proc. IEEE Custom Integrated Circuits Conf., 2008.Google Scholar
[15] Thacker, H. Ogunsola, O. Carson, A. Bakir, M. and Meindl, J. “Optical through-wafer interconnects for 3D hyper-integration,” in Proc. IEEE Lasers & Electro-Optics Society Annual Meeting, 2006, pp. 28–29.Google Scholar
[16] Bakir, M. S. Dang, B. and Meindl, J. D. “Revolutionary nanosilicon ancillary technologies for ultimate-performance gigascale systems,” in Proc. IEEE Custom Integrated Circuits Conf., 2007, pp. 421–428.Google Scholar
[17] Bakir, M. S. Glebov, A. L. Lee, M. G. Kohl, P. A. and Meindl, J. D. “Mechanically Flexible Chip-to-Substrate Optical Interconnections Using Optical Pillars,” IEEE Trans. on Advanced Packaging, vol. 31, pp. 143–153, 2008.Google Scholar
[18] Glebov, A. L. Bhusari, D. Kohl, P. Bakir, M. S. Meindl, J. D. and Lee, M. G. “Flexible pillars for displacement compensation in optical chip assembly,” IEEE Photonics Technol. Lett., vol. 18, pp. 974–976, 2006.Google Scholar
[19] Dang, B. “Integrated Input/Output Interconnection and Packaging for GSI,” Ph. D. Thesis, Georgia Institute of Technology, 2006.Google Scholar
[20] Zhang, H. Y. Pinjala, D. Wong, T. N. and Joshi, Y. K. “Development of liquid cooling techniques for flip chip ball grid array packages with High Heat flux dissipations,” IEEE Trans. Components and Packaging Technol., vol. 28, pp. 127–135, 2005.Google Scholar
[21] Colgan, E. G. Furman, B. Gaynes, A. Graham, W. LaBianca, N. Magerlein, J. H. Polastre, R. J., Rothwell, M. B. Bezama, R. J. Choudhary, R. Marston, K. Toy, H. Wakil, J. and Zitz, J. “A practical implementation of silicon microchannel coolers for high power chips,” in Proc. IEEE Semiconductor Thermal Measurement and Management Symp., 2005, pp. 1–7.Google Scholar
[22] Tuckerman, D. B. and Pease, R. F. W. “High-performance heat sinking for VLSI,” IEEE Electron Dev. Lett., vol. 2, pp. 126–129, 1981.Google Scholar
[23] Wu, J. H. Scholvin, J. and Alamo, J. A. del, “A through-wafer interconnect in silicon for RFICs,” IEEE Trans. Electron Devices, vol. 51, pp. 1765–1771, 2004.Google Scholar
[24] Meindl, J. D. “Low power microelectronics: retrospect and prospect,” Proceedings of IEEE, vol. 83, pp. 619–635, Apr. 1995.Google Scholar
[25] Swaminathan, M. and Engin, E. Power Integrity: Modeling and Design for Semiconductor and Systems, Prentice Hall, 1st Edition, 2007.Google Scholar
[26] Zheng, H. Krauter, B. and Pileggi, L.T. “Electrical modeling of integrated-package power/ground distributions,” IEEE Design and Test of Computer, vol. 20, no. 3, pp. 23–31, May-June, 2003.Google Scholar
[27] Wong, K. L. Rahal-Arabi, T., Ma, M. and Taylor, G. “Enhancing microprocessor immunity to power supply noise with clock-data compensation,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, April, 2006.Google Scholar
[28] Becker, W. D. Eckhardt, J. Frech, R. W. Katopis, G. A. Klink, E. McAllister, M. F. MacNamara, T. G., Muench, P. Richter, S. R. and Smith, H. H. “Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, part B, vol. 21, pp. 157–163, May 1998.Google Scholar
[29] Dharchoudhury, A. Panda, R. Blaauw, D. Vaidyanathan, R. “Design and analysis of power distribution networks in PowerPC microprocessors,” in Proc. IEEE Design Automation Conf., 15-19 June 1998 pp: 738–743.Google Scholar