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Trapping in low-κ dielectric for interconnects was highlighted by voltage shift in IV current-voltage measurements. It is shown that effects of trapping can impact the extraction of conduction mechanisms. Capacitance measurements made on these materials reveal that trapping is at the origin in the increase of capacitance. The creation of dipoles because of this trapping explains this increase in the value of capacitance.
High yielding and high strength Cu-Cu thermo-compression bonds have been obtained at temperatures as low as 175°C. Plated Cu bumps are used for bonding, without any surface planarization step or plasma treatment, and bonding is performed at atmospheric condition. In this work the 25μm diameter bumps are used at a bump pitch of 100μm and 40μm. Low temperature bonding is achieved by using immersion bonding in citric acid. Citric acid provides in-situ cleaning of the Cu surface during the bonding process. The daisy chain electrical bonding yield ranges from 84%-100% depending on the bonding temperature and pressure.
Nanoporous organosilicate films have been recently prepared using tetraalkylammonium cations in acid and basic media, outperforming other materials. Resulting films using basic medium were called zeolite-inspired low-k dielectrics. Here we study the dependence of the properties of these films on the used silica sources: methyltrimethoxy silane (MTMS) and tetraethyl orthosilicate (TEOS). A set of experiments varying the MTMS:TEOS ratio were prepared in acid medium and characterized. A textural, physico-chemical, mechanical, and electrical characterization of this series of experiments is presented.
A thin-amorphous MnOx layer using self-forming barrier process with a Cu-Mn alloy shows good adhesion and diffusion barrier properties between copper and dielectric layer, resulting in excellent reliability for stress and electromigration. Meanwhile, chemical vapor deposition (CVD) can be employed for conformal deposition of the barrier layer in narrow trenches and vias for future technology node. In our previous research, a thin and uniform amorphous MnOx layer could be formed on TEOS-oxide by thermal metal-organic CVD (MOCVD), showing a good diffusion barrier property. In addition, a good adhesion strength is necessary between a Cu line and a dielectric layer not only to ensure good SM and EM resistance but also to prevent film delamination under mechanical or thermal stress conditions during fabrication process such as chemical mechanical polishing or high temperature annealing. To date, no information is available with regard to the adhesion property of CVD-MnOx. In this work, we report diffusion barrier property in further detail and adhesion property in PVD-Cu/CVD-MnOx/SiO2/Si. The temperature dependence of the adhesion property is correlated with the chemical composition and valence state of Mn investigated with SIMS and Raman spectroscopy.
Substrates were p-type Si wafers having a plasma-TEOS oxide of 100nm in thickness. CVD was carried out in a deposition chamber. A manganese precursor was vaporized and introduced into the deposition chamber with H2 carrier gas. After the CVD, a Cu overlayer was deposited on some samples using a sputtering system in load lock chamber of the CVD machine. The diffusion barrier property of the MnOx film was investigated in annealed samples at 400 oC for 100 hours in a vacuum of better than 1.0×10-5 Pa. The Adhesion property of Mn oxide was investigated by Scotch tape test in the as-deposited and in the annealed Cu/CVD-MnOx/TEOS samples. The obtained samples were analyzed for thickness and microstructure with TEM, chemical bonding states of the MnOx layer with XPS, and composition of each layer with SIMS.
In the CVD deposition below 300 °C, no Cu delamination was observed both in the as-deposited and in the annealed Cu/CVD-MnOx/SiO2 samples. On the other hand, in the CVD deposition at 400 °C, the Cu films were delaminated from the CVD-MnOx/TEOS substrates. The XPS peak position of Mn 2p and Mn 3s spectra indicated that the valence state of Mn in the as-deposited barrier layer below 400 °C was 2+. Composition analysis with SIMS as well as Raman also indicated the presence of a larger amount of carbon at 400 °C than at less than 300 °C. The good adhesion between Cu and MnO could be attributed to an amount of carbon inclusion in the CVD barrier layer.
Glancing-incidence X-ray diffraction (GIXRD) has been applied to the investigation of depth-dependent stress distributions within electroplated Cu films due to overlying capping layers. 0.65 μm thick Cu films plated on conventional barrier and seed layers received a CVD SiCxNyHz cap, an electrolessly-deposited CoWP layer, or a CoWP layer followed by a SiCxNyHz cap. GIXRD and conventional X-ray diffraction measurements revealed that strain gradients were created in Cu films possessing a SiCxNyHz cap, where a greater in-plane tensile stress was generated near the film / cap interface. The constraint imposed by the SiCxNyHz layer during cooling from the cap deposition temperature led to an increase in the in-plane stress of approximately 180 MPa from the value measured in the bulk Cu. However, Cu films possessing a CoWP cap without a SiCxNyHz layer did not exhibit depth-dependent stress distributions. Because the CoWP capping deposition temperature was much lower than that employed in SiCxNyHz deposition, the Cu experienced elastic deformation during the capping process. Cross-sectional transmission electron microscopy indicated that the top surface of the Cu films exhibited extrusions near grain boundaries for the samples undergoing the thermal excursion during SiCxNyHz deposition. The conformal nature of these caps confirmed that the morphological changes of the Cu film surface occurred prior to capping and are a consequence of the thermal excursions associated with cap deposition.
The effect of He plasma pretreatment on interaction of O and H atoms with SiCOH low-k materials is studied using a special experimental system designed for this purpose. The experimental system allowed separate study of the effects of He plasma, VUV light and He 21S0 metastable atoms. It is shown that the carbon depletion by oxygen atoms can be significantly reduced by He plasma pretreatment. Considerable increase of CH and CH2-CH2 groups in the surface area of low-k films is observed when the films were exposed to VUV light and metastable atoms generated by He plasma. FTIR and ellipsometry showed formation of densified surface layer. This carbon rich densified surface layer decreases damage of low-k film when it is exposed in O2 plasma. The impact of H atoms on low-K surface noticeably differs from O atoms effect. The H atoms saturate all unbounded remaining carbon bonds thereby promoting improvement of SiOCH structure.
The paper addresses grain growth in copper interconnects in the presence of thermal expansion mismatch stresses. The evolution of grain structure and texture in copper in the simultaneous presence of two driving forces, curvature and elastic stored energy difference, is modeled by using a hybrid Potts model simulation approach. The elastic stored energy is calculated by using the commercial finite element code ABAQUS, where the effect of elastic anisotropy on the thermal mismatch stress and strain distribution within a polycrystalline grain structure is modeled through a user material (UMAT) interface. Parametric studies on the effect of trench width and the height of the overburden were carried out. The results show that the grain structure and texture evolution are significantly altered by the presence of elastic strain energy.
Atomic Layer deposition of thin Ruthenium films has been studied using a newly synthesized precursor (Cyclopentadienyl ethylruthenium dicarbonyl) and O2 as reactant gases. Under our experimental conditions, the film comprises both Ru and RuO2. The initial growth is dominated by Ru metal. As the number of cycles is increased, RuO2 appears. From infrared broadband absorption measurements, the transition from isolated, nucleated film to a continuous, conducting film (characterized by Drude absorption) can be determined. Optical simulations based on an effective-medium approach are implemented to simulate the in-situ broadband infrared absorption. A Lorentz oscillator model is developed, together with a Drude term for the metallic component, to describe optical properties of Ru/RuO2 growth.
A new fabrication technique to prepare ultra-thin barrier layers for nano-scale Cu wires was proposed in our previous studies. Ti-rich layers formed at the Cu(Ti)/dielectric-layer interfaces consisted of crystalline TiC or TiSi and amorphous Ti oxides. The primary control factor for Ti-rich interface layer composition was the C concentration in the dielectric layers rather than the formation enthalpy of the Ti compounds. To investigate Ti-rich interface layer growth in Cu(Ti)/dielectric-layer samples annealed in ultra high vacuum, Rutherford Backscattering Spectrometry (RBS) was employed in the present study. Ti peaks were obtained only at the interface for all the samples. Molar amounts of Ti atoms segregated to the interface (n) were estimated from Ti peak areas. The n value was defined by n = Z·exp(-E/RT) · tm, where Z is a preexponential factor and E the activation energy for the reaction. The Z, E, and m values were estimated from plots of log n vs log t and log n vs 1/T. The m values are similar in all the samples. The E values for Ti atoms reacting with the dielectric layers containing carbon (except SiO2) tended to decrease with decreasing C concentration (decreasing k), while reaction rate coefficients (Z·exp(-E/RT)) were insensitive to C concentration in the dielectric layers. These factors lead to conclusion that growth of the Ti-rich interface layers is controlled by chemical reactions of the Ti atoms with the dielectric layers represented by the Z and E values, rather than diffusion in the Ti-rich interface layers.
In high frequency signal packaging, the plastic dielectric material takes on an increasingly important role in the performance of the signal transmission. Variations within the plastic can occur as a result of a number of manufacturing and environmental processes. These variations can be sufficient to change the dielectric properties. The extent of change to the dielectric properties of polymer materials as a result of controlled variations to major filler additives, moisture and temperature has been investigated. The combined effects of moisture and temperature can cause changes to the dielectric constant of certain materials by more than 30 %.
A supercritical fluid is a high-pressure medium that possesses both high diffusivity and solvent capabilities. Metal thin films can be deposited in supercritical fluids from an organometallic compound (precursor) through thermochemical reactions. In the present study, we used a technique, aimed at applying to the fabrication of through-silicon vias (TSVs), where copper thin films were deposited in silicon microholes 10 μm in diameter and 350 μm in depth. The temperature and pressure were varied from 180°C to 280°C and 1 MPa to 20 MPa, respectively. The maximum coating depth decreased with deposition temperature, whereas a peak maximum of the depth was observed at around 10 MPa. The temperature and pressure dependences on the coating depth were numerically studied. On the basis of the analysis, a deposition program was modified as to elongate the coating depth.
An alternative bottom-up Cu electro-less deposition (ELD) method without other catalyst material activation tested on blanket wafers, is the focus of this paper. The process consists in reducing the Cu ions via standard reducing agents, such as dimethylamine borane (DMAB). A wide range of experimental conditions such as pH, temperature, Cu ion concentration and time are investigated and the Cu layer nucleation and growth mechanism is evaluated on clean SiO2 and after functionalization with 3-aminopropyltrimethoxysilane (APTS) self-assembled monolayer (SAM) used as copper diffusion barrier. The barrier properties of the APTS layer after Cu ELD are also assessed by copper resistivity measurements and visual inspections as a function of the annealing temperature.
At 65nm and beyond technology nodes, copper interconnect formation in dual damascene integration is continually challenged from a polymer management perspective. Highly polymeric plasma chemistry is required to reduce line edge roughness, shape physical profile, and control critical dimension across a 300mm wafer. But too much fluorocarbon deposition on a wafer results in poor defects yield.
In this paper, X-ray photoelectron spectroscopy (XPS) characterization technique is used to quantify and to optimize a metal line reactive ion etch process to increase electrical opens yield. A reduction of 2 at.% in carbon mass results in a Do (defects/cm2) improvement from > 2.0 to less than 1.0. This result is realized without a shift to the trench physical profile which is important for reliability performance. Moreover, with a shorter turnaround time of XPS characterization compared to electrical hardware splits, quicker yield learning cycle is realized for both RIE process and module integration.
We evaluated Triangular Voltage Sweep (TVS) measurements as a technique to characterize plasma damage in low-k films. Blanket wafers with low-k films of different porosity and k value were prepared. Our samples included an SiOC:H material with 7% porosity and k value of 3.0, deposited on 200mm wafers, and two SiOC:H materials with 25% porosity and k value of 2.5, deposited on 300mm wafers. Before deposition, a thin layer of dry thermal oxide (2 – 5 nm) was grown on the n-type wafers to stabilize the silicon interface. After deposition, low-k films were exposed to N2/H2 plasma for different times in order to induce different degree of plasma damage. Untreated low-k films were always included as a reference. For electrical measurements, metal dots were deposited on pieces to fabricate Metal-Insulator-Semiconductor capacitors.
TVS measurements were performed at 190°C on the different samples. On samples exposed to N2/H2 plasma, we detected a current peak in the TVS trace, whose magnitude increased with exposure time to plasma. No peaks were detected on untreated films. This indicates that TVS measurements are sensitive to plasma damage. Furthermore, TVS results correlated well with FTIR spectra that showed increasing damage and H2O uptake with increasing exposure time to plasma. We conclude that TVS measurements are suitable for characterizing the degree of plasma damage in low-k films and complement well materials analysis, because with the help of TVS a link to leakage properties can be made. As an application, we used TVS measurements for evaluating restoration of plasma damaged low-k films by long N2-bake at high temperature. Wafer pieces from each sample were baked at 350°C for 4h30min in N2 atmosphere. A few pieces were measured immediately after baking. The remaining pieces were either left exposed to ambient for a few days or dipped in deionized H2O for a few hours to evaluate recovery of hydrophobic properties. The different treatments (N2-bake, exposure to ambient, H2O dipping) were always performed on blanket wafer pieces. Metal dots for electrical measurements were only deposited after the treatment. CV and FTIR measurements were performed before and after treatments to evaluate change in k-value and material structure, respectively. Our data show that long N2-bake at high temperature can partially restore damaged low-k films. The magnitude of the damage-related TVS peak was significantly reduced after heat treatment and remained stable even after H2O dipping. CV measurements performed on baked pieces after 6 days of exposure to ambient showed a reduced k-value. Consistently, FTIR spectra showed a significant reduction of H2O content soon after baking. The materials remained stable over several days and only minor reincorporation of H2O occurred after exposure to ambient or H2O dipping. Therefore, long N2-bake at high temperature can partially restore leakage (TVS), k-value (CV) and hydrophobic properties (FTIR) of damaged low-k films.
This paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.
This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.
In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.
This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.
Even after the successful introduction of Cu-based metallization, the electromigration failure risk has remained one of the important reliability concerns for advanced process technologies. The observation of strong bimodality for the electron up-flow direction in dual-inlaid Cu interconnects has added complexity, but is now widely accepted. More recently, bimodality has been reported also in down-flow electromigration, leading to very short lifetimes due to small, slit-shaped voids under vias. For a more thorough investigation of these early failure phenomena, specific test structures were designed based on the Wheatstone Bridge technique. The use of these structures enabled an increase of the tested sample size past 1.1 million, allowing a direct analysis of electromigration failure mechanisms at the single-digit ppm regime. Results indicate that down-flow electromigration exhibits bimodality at very small percentage levels, not readily identifiable with standard testing methods. The activation energy for the down-flow early failure mechanism was determined to be 0.83 ± 0.01 eV. Within the small error bounds of this large-scale statistical experiment, this value is deemed to be significantly lower than the usually reported activation energy of 0.90 eV for electromigration-induced diffusion along Cu/SiCN interfaces. Due to the advantages of the Wheatstone Bridge technique, we were also able to expand the experimental temperature range down to 150 °C, coming quite close to typical operating conditions up to 125 °C. As a result of the lowered activation energy, we conclude that the down-flow early failure mode may control the chip lifetime at operating conditions. The slit-like character of the early failure void morphology also raises concerns about the validity of the Blech-effect for this mechanism. A very small amount of Cu depletion may cause failure even before a stress gradient is established. We therefore conducted large-scale statistical experiments close to the critical current density-length product (jL)*. The results indicate that even at very small failure percentages, this critical product seems to extrapolate to about 2900 ± 400 A/cm for SiCOH-based dielectrics, close to previously determined (jL)* products of about 3000 ± 500 A/cm for the same technology node and dielectric material, acquired with single link interconnects. More detailed studies are currently ongoing to verify the extrapolation methods at small percentages. Furthermore, the scaling behavior of the early failure population was investigated.
Diffusion barrier characteristics of amorphous and polycrystalline electroless Co(W,P) layers (α-Co(W,P) and poly-Co(W,P)) to lead-free SnAgCu (SAC) solder were investigated via the liquid- and solid-state aging tests. In the sample containing α-Co(W,P) subjected to liquid-state aging at 250°C for 1 hr, the spallation of (Co,Cu)Sn3 intermetallic compound (IMC) into the solder and formation of a polycrystalline P-rich layer in between SAC and Co(W,P) were found. Further, the α-Co(W,P) transforms into polycrystalline structure embedded with tiny Co2P precipitates As to the sample containing α-Co(W,P) subjected to solid-state aging at 150°C up to 1000 hrs, a thick (Cu,Co)6Sn5 IMC resided in between SAC and Co(W,P) and the P-rich layer beneath IMCs was similarly seen. In the samples containing poly-Co(W,P) subjected to liquid-state aging, a mixture of (Co,Cu)Sn3 and (Co,Ag)Sn3 IMCs formed in between SAC and Co(W,P). An amorphous W-rich layer formed in between SAC and poly-Co(W,P). Similar interfacial morphology was observed in the samples subjected to the solid-state aging test. Analytical results indicated the electroless Co(W,P) is in essential a combined-type, i.e., sacrificial-type plus stuffed-type, diffusion barrier. However, the α-Co(W,P) is a better diffusion barrier for under bump metallurgy (UBM) applications in flip-chip (FC) bonding since it exhibits a lower Co consumption rate in comparison with poly-Co(W,P).
In this study, intralevel dielectric breakdown is studied for copper interconnects in an SiOF dielectric, capped with either SiN or SiCN. The leakage current is higher and the failure time of dielectric breakdown is shorter for an SiCN capping layer compared to an SiN capping layer. It is proposed that the dielectric breakdown of the integrated structure is limited by the interface between the capping layer and the SiOF dielectric. Lower lifetime for dielectric breakdown is observed for structures with an SiCN cap compared to structures with an SiN cap, due to higher leakage current in the SiCN. The higher leakage for an SiCN cap is consistent with results from planar metal-insulator-semiconductor capacitors.
An ultrathin barrier layer of MnOx was grown using metal organic chemical vapor deposition (MOCVD) at an interface between Cu and SiO2 dielectric. The electronic transport properties of Cu/MnOx/SiO2/p-Si metal oxide semiconductor (MOS) devices showed leakage current density within the range of 10-8-10-7A/cm2 up to an electric field of 4MV/cm. The current density remained within the same range after bias temperature aging test at 3MV/cm for 6×103s at 550K. The capacitance-voltage curves of the MOS device having the MnOx layer grown at 473K do not show significant shift of flat band voltage after thermal annealing at 673K for 3.6×103s as well as after bias temperature aging test at 1MV/cm, 550K for 2.4×103 s. These results indicate that the ultrathin layer of MnOx is stable under the above conditions and prevents sufficiently Cu ion diffusion into the SiO2 dielectric.
The results of recent investigations show that after UV curing of CVD SiCOH low-k films deposited with organic material (porogen) some amount of the porogen remains in the cured films in the form of non-volatile graphitized phase, known as “porogen residue”. These residues could influence leakage current and reliability. The goal of the present work is investigation of the different parameters of UV curing that can influence amount of the porogen residue. In this work we focused generally on the study of the amount of porogen residues as function of the wavelength of curing light and the porosity of the material (amount of deposited porogen). To study the curing dependence on the wavelength, we compared optical properties (measured by spectroscopic ellipsometry) and IR adsorption (measured by FTIR) of samples cured by 172 nm monochromatic light (lamp A) with samples cured by broadband source with wavelength more than 200 nm (lamp B). To understand how the amount of porogen residue depends on the amount of deposited porogen (porosity), three films with different k-value were deposited: a film with k = 3 deposited without porogen and two porogen-based low-k with target k-value of 2.5 and 2.3. Furthermore, taking into account that He/H2 plasma effectively removes the porogen residues from porous films without any plasma damage of the matrix material, we exposed the films to that plasma. Then these films were cured by broadband lamp at different temperatures and amount of porogen residues was measured by ellipsometry. It was found that He/H2 plasma cannot fully remove the porogen and causes film shrinkage. The Subsequent UV curing does not produce significant changes.