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High Mobility Channel Materials and Novel Devices for Scaling of Nanoelectronics beyond the Si Roadmap

Published online by Cambridge University Press:  31 January 2011

Marc Heyns
Affiliation:, imec, Leuven, Belgium
Florence Bellenger
Affiliation:, imec, Leuven, Belgium
Guy Brammertz
Affiliation:, imec, Leuven, Belgium
Matty Caymax
Affiliation:, imec, Leuven, Belgium
Stefan De Gendt
Affiliation:, imec, Leuven, Belgium
Brice De Jaeger
Affiliation:, imec, Leuven, Belgium
Annelies Delabie
Affiliation:, imec, Leuven, Belgium
Geert Eneman
Affiliation:, imec, Leuven, Belgium
Guido Groeseneken
Affiliation:, imec, Leuven, Belgium
Michel Houssa
Affiliation:, KULeuven, Leuven, Belgium
Daniele Leonelli
Affiliation:, imec, Leuven, Belgium
Dennis Lin
Affiliation:, imec, Leuven, Belgium
Koen Martens
Affiliation:, imec, Leuven, Belgium
Clement Merckling
Affiliation:, imec, Leuven, Belgium
Marc Meuris
Affiliation:, imec, Leuven, Belgium
Jerome Mitard
Affiliation:, imec, Leuven, Belgium
Julien Penaud
Affiliation:, Riber, Leuven, Belgium
Geoffrey Pourtois
Affiliation:, imec, Leuven, Belgium
Marco Scarrozza
Affiliation:, imec, Leuven, Belgium
Eddy Simoen
Affiliation:, imec, Leuven, Belgium
Sven Van Elshocht
Affiliation:, imec, Leuven, Belgium
William Vandenberghe
Affiliation:, imec, Leuven, Belgium
Anne Vandooren
Affiliation:, imec, Leuven, Belgium
Wei-E Wang
Affiliation:, INTEL, Leuven, Belgium
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High mobility channel materials and new device structures will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of Ge and III/V materials and novel devices such as heterojunction TunnelFET’s is investigated for future CMOS applications. High-performance CMOS can be obtained by combining Ge pMOS devices with nMOS devices made on III/V compounds such as InGaAs. In all cases the key challenge is the electrical passivation of the interface between the high-k dielectric and the alternative channel materials. Recent studies have demonstrated good electrical properties of the GeO2/Ge interface. Since the GeO2 layer is very hygroscopic, full in-situ processing of GeO2 formation and high-k deposition must be performed or other methods must be employed to stabilize the GeO2 layer. One of the most successful passivation techniques for Ge MOS gate stacks is a thin, epitaxial layer of Si. A lot of attention went into better understanding of this passivation and the effects of its optimization on various device characteristics. It was found that mobility and Vt trends in both pMOS and nMOS transistors can be explained based on defects located at the Si/SiO2 interface. Unfortunately, III-V/oxide interfaces are not quite as robust and most interfaces present rather high densities of interface states. Although, considerable improvements have been realized in the reduction of the interface state density, further developments are required to obtain high performance MOS devices. To this purpose various passivation methods were critically evaluated. Simulations using Density Functional Theory reveal the possibility of using a thin amorphous layer made of GeOX to obtain an electrically unpinned gap. The major challenge resides in the control of the c-Ge thickness and the oxidation of this layer to avoid the diffusion of oxygen atoms at the Ge/GaAs(001) interface. Promising results are obtained by optimizing the surface preparation, high-k deposition and annealing cycle on In0.53Ga0.47As-Al2O3 interfaces. Self-aligned inversion channel n-MOSFETs fabricated on p-type In0.53Ga0.47As demonstrate inversion-mode operation with high drive current and a peak electron mobility of 3000 cm2/Vs. Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts. Novel structures such as heterojunction TunnelFET’s can fully exploit the properties of these new materials and provide superior performance at lower power consumption by virtue of their improved subthreshold behaviour. Vertical surround gate devices produced from nanowires allow the introduction of a wide range of materials on Si. This illustrates the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.

Research Article
Copyright © Materials Research Society 2010

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