The reliability of integrated-circuit wiring depends strongly on the development and relaxation of stresses that promote void and hillock formation. In this paper an analysis based on existing models of creep is presented that predicts the stresses developed in thin blanket films of copper on Si wafers subjected to thermal cycling. The results are portrayed on deformation-mechanism maps that identify the dominant mechanisms expected to operate during thermal cycling. These predictions are compared with temperature-ramped and isothermal stress measurements for a 1 μm-thick sputtered Cu film in the temperature range 25–450 °C. The models successfully predict both the rate of stress relaxation when the film is held at a constant temperature and the stress-temperature hysteresis generated during thermal cycling. For 1 μm-thick Cu films cycled in the temperature range 25–450 °C, the deformation maps indicate that grain-boundary diffusion controls the stress relief at higher temperatures (>300 °C) when only a low stress can be sustained in the films, power-law creep is important at intermediate temperatures and determines the maximum compressive stress, and that if yield by dislocation glide (low-temperature plasticity) occurs, it will do so only at the lowest temperatures (<100 °C). This last mechanism did not appear to be operating in the film studied for this project.