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Appropriate passivation structure in dynamic random access memory devices to improve stress-related reliability performance after plastic packaging

Published online by Cambridge University Press:  31 January 2011

Seong-Min Lee
Seong-Min Lee
Affiliation:
Department of Materials Science & Engineering, University of Inchon, 177 Dohwa-dong, Nam-Ku, Inchon 402-749, South Korea
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This work attempts to determine an appropriate passivation structure in the real integrated circuit (IC) pattern to improve stress-related reliability problems after the plastic packaging. Several different types of amorphous passivation materials were first tested to learn how effectively they protect underlying Al interconnection lines during thermal displacement-induced fatigue at temperature ranges from −65 °C to 150 °C. It was also studied how effectively the occurrence of cracking in a passivation layer can be suppressed by the improvement of its topological feature or increase in its thickness. According to the experimental results, an increase in passivation thickness up to 21,000 Å (7000 Å for oxide and 14,000 Å for SiN, respectively) was found to be a highly effective way to suppress stress-induced passivation damage on the inside of the chip in plastic IC packages. However, at the edges of the chip, smoothing of the passivation layer by a sloping metal sidewall was more important for the improvement of thermal cycling performance than thickening of the passivation layer.

Type
Articles
Information
Journal of Materials Research , Volume 13 , Issue 7 , July 1998 , pp. 1967 - 1973
Copyright
Copyright © Materials Research Society 1998

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