Introduction

In Sections 11.1 and 11.2, we introduced some notions of behavioural equivalence over real-time systems specified by means of timed automata. These equivalences are based on various adaptations to the timed setting of the classic notions of trace equivalence and bisimilarity over LTSs – as presented in Sections 3.2 and 3.3 of this book – and may be used to perform implementation verification for real-time systems. This is useful because, at least in principle, a formalism like that of timed automata can be used to describe both actual systems and their specifications and, as we saw in Section 11.6, these notions of behavioural equivalence are decidable over (networks) of timed automata, with the notable exception of timed trace equivalence.

However, as we have already noted in the setting of modelling and verification for classic untimed reactive systems, when establishing the correctness of our system with respect to a specification using the methodology of implementation verification, we are forced to specify in some way the overall behaviour of the system under consideration. In a real-time setting, this often means that our specifications need to take into account many details pertaining to the timing behaviour of the implementation under analysis. This may lead to overly complex and subtle specifications. Moreover, sometimes we are interested only in specifying the expected behaviour of the system in certain specific circumstances.