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  • Print publication year: 2011
  • Online publication date: October 2011

5 - The large-signal model: theoretical foundations, practical considerations, and recent trends



This chapter presents a survey of selected theoretical foundations of large-signal device modeling for nonlinear circuit simulation. Topics covered include conditions for well-defined nonlinear constitutive relations, nonlinear charge modeling including a comprehensive discussion of terminal charge conservation, and also diffusion charge, transit time, and capacitance cancelation modeling in III–V HBTs. Practical considerations are presented for regularizing poorly defined constitutive relations, constructing and using nonlinear table-based models, and extrapolating measurement-based models for robust convergence. Recent advances in nonlinear measurement instrumentation, specifically the commercial availability of the nonlinear vector network analyzer (NVNA), and the growing sophistication of artificial neural networks for device modeling, are simultaneously exploited to develop an advanced electrothermal and trap-dependent III–V FET model constructed directly from large-signal data.

The equivalent circuit

Intrinsic and extrinsic elements

The separation of a circuit-level transistor model into intrinsic and extrinsic parts is an idealization that simplifies the treatment of an otherwise very complicated device. Equivalent circuits of a simple quasi-static III–V FET model [1] and a modern III–V HBT model [2–4] are shown in Figure 5.1 and Figure 5.2, respectively.

Conceptually, the intrinsic model describes the dominant nonlinearities of the transistor that occur in the active region, inside the feed networks, manifolds, and other parasitic particularities of the layout. For FETs, the intrinsic model includes that part of the active drain-source channel controlled by the gate and modulated by gate–source and drain–source voltages.

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[1] Curtice, W. R. and Ettenberg, M., “A nonlinear GaAs FET model for sse in the design of output circuits for power amplifiers,” IEEE Trans. Microw. Theory Tech, vol. 33, pp. 1383–1394, Dec. 1985.
[2] ,Agilent heterojunction bipolar transistor model (AHBT), Agilent Advanced Design System Manual, nonlinear devices, ch. 2.
[3] Iwamoto, M. and Root, D. E., “Large-signal III–V HBT model with improved collector transit time formulations, dynamic self-heating, and thermal coupling,” Int.Workshop on Nonlinear Microw. and Millimeter Wave Integrated Circuits (INMMIC), Rome, Nov. 2004.
[4] Iwamoto, M. and Root, D. E., “Agilent HBT model overview,” Compact Model Council Meeting, San Francisco, CA, Dec. 2006. Available:
[5] Nedeljkovic, S., Gering, J., Kharabi, F., McMacken, J., Clausen, B., Partyka, P., and Parker, S., “Extrinsic parameter and parasitic elements in III–V HBT and HEMT modeling,” Nonlinear Transistor Parameter Extraction Techniques, Rudolph, M., Root, D. E., Fager, C., Eds., Cambridge Univ. Press, ch. 3.
[6] Wood, J. and Root, D. E., “Bias-dependent linear scalable millimeter-wave FET model,” IEEE Trans. Microw. Theory Tech., vol. 48, pp. 2352–2360, Dec. 2000.
[7] Iwamoto, M., Xu, J., and Root, D. E., “DC and thermal modeling for III–V FETs and HBTs,” in Nonlinear Transistor Parameter Extraction Techniques, Rudolph, M., Fager, C., Root, D. E., Eds., Cambridge Univ. Press, ch. 2.
[8] Kirkpatrick, S., Gelett, C. D., and Vecchi, M. P., “Optimization by simulated annealing,” Sci. vol. 220. pp. 621–680, May 1983.
[9] Root, D. E. “Overview of microwave FET modeling for MMIC design, charge modeling and conservation laws, and advanced topics,” 1999 Asia Pacific Microw. Conf. Workshop Short Course on Modeling and Characterization of Microw. Devices and Packages, Singapore, Nov. 1999.
[10] Root, D. E., “Principles and procedures for successful large-signal measurement-based FET modeling for power amplifier design,” Nov. 2000. Available: http://cp.literature.
[11] Maas, S., “Fixing the Curtice FET model,” Microw. J., Mar. 2001.
[12] Antoun, G., El-Nozahi, M., and Fikry, W., “A hybrid genetic algorithm for MOSFET parameter extraction,” IEEE CCECE, vol. 2, May 2003, pp. 1111–1114.
[13] Root, D. E.Measurement-based mathematical active device modeling for high frequency circuit simulation,” IEICE Trans. Electron. vol. E82-C, pp. 924–936, June 1999.
[14] McGinty, D. J., Root, D. E., and Perdomo, J., “A production FET modeling and library generation system,” in IEEE GaAs MANTECH Conf. Tech. Dig., San Francisco, CA, July 1997 pp. 145–148.
[15] Akhtar, S., Roblin, P., Lee, S., Ding, X., Yu, S., Kasick, J., and Strahler, J., “RF electro-thermal modeling of LDMOSFETs for power-amplifier design,” IEEE Trans. Microw. Theory Tech., vol. 50, pp. 1561–1570, Jun., 2002.
[16] Coughran, W. M., Fichtner, W., and Grosse, E., “Extracting transistor charges from device simulations by gradient fitting,” IEEE Trans. Electron Devices, vol. 8 pp. 380–394, 1989.
[17] Cuoco, V., Heijden, M. P., and Vreede, L. C. N, “The ‘Smoothie’ data base model for the correct modeling of non-linear distortion in FET devices,” IEEE Int. Microw. Symp. Dig., vol. 3, pp. 2149–2152, 2002.
[18] Root, D. E., Fan, S., and Meyer, J., “Technology independent non quasi-static FET models by direct construction from automatically characterized device data,” 21st Eur. Microw. Conf. Proc., Stuttgart, Germany, pp. 927–932, Sept. 1991.
[19] Agilent 85190A IC-CAP Manual, nonlinear device models, vol. 2, ch. 1.
[20] Xu, J., Gunyan, D., Iwamoto, M., Cognata, A., and Root, D. E., “Measurement-based non-quasistatic large-signal FET model using artificial neural networks,” IEEE Int. Microw. Symp. Dig., pp. 469–472, June 2006.
[21] Xu, J., Gunyan, D., Iwamoto, M., Horn, J., Cognata, A., and Root, D. E., “Drain-source symmetric artificial neural network-based FET model with robust extrapolation beyond training data,” IEEE Int. Microw. Symp. Dig., June 2007.
[22] Wood, J., Aaen, P. H., Bridges, D., Lamey, D., Guyonnet, M., Chan, D. S., and Monsauret, N., “A nonlinear electro-thermal scalable model for high-power RF LDMOS transistors,” IEEE Trans. Microw. Theory Tech., vol. 57, pp. 282–292, Feb. 2009.
[23] Xu, J., Horn, J., Iwamoto, M., and Root, D. E., “Large-signal FET model with multiple time scale dynamics from nonlinear vector network analyzer data,” IEEE Int. Microw. Symp. Dig., May, 2010.
[24] Haykin, S., Neural Networks: A Comprehensive Foundation (2nd ed.). Prentice Hall, 1998.
[25] Zhang, Q. J. and Gupta, K. C., Neural Networks for RF and Microwave Design. Artech House, 2000.
[26] Matlab Neural Network Toolbox™
[27] Xu, J., Yagoub, M. C. E., Runtao, D., and Zhang, Q. J., “Exact adjoint sensitivity analysis for neural-based microwave modeling and design,” IEEE Trans. Microw. Theory Tech., vol. 51, pp. 226–237 Jan. 2003.
[28] Pekker, A., Root, D. E., and Wood, J., “Simulating operation of an electronic circuit,” US patent application #20050251376 A1, May 10, 2004.
[29] Barber, C. B., Dobkin, D. P., and Huhdanpaa, H. T., “The Quickhull algorithm for convex hulls,” ACM Trans. on Math. Software, vol. 22, pp. 469–483, Dec. 1996.
[30] Zhang, L. and Zhang, Q. J., “Simple and effective extrapolation technique for neural-based microwave modeling,” IEEE Microw. and Wireless Components Lett., vol 20, pp. 301–303, June 2010.
[31] Root, D. E., “Measurement-based active device modeling for circuit simulation,” Eur. Microw. Conf. Advanced Microw. Devices, Characterization, and Modeling Workshop, Madrid, Sept. 1993 (available from author).
[32] Staudinger, J., Baca, M. C., and Vaitkus, R., “An examination of several large signal capacitance models to predict GaAs HEMT linear power amplifier performance,” IEEE Radio and Wireless Conf., Aug. 1998, pp. 343–346.
[33] Root, D. E., “Nonlinear charge modeling for FET large-signal simulation and its importance for IP3 and ACPR in communication circuits,” Proc. 44th IEEE Midwest Symp. on Circuits and Sys., Dayton OH, Aug. 2001, pp. 768–772 (corrected version available from author)
[34] Rudolph, M., Introduction to Modeling HBTs. Norwood, MA: Artech House, 2006.
[35] Iwamoto, M., Asbeck, P. M., Low, T. S., Hutchinson, C. P., Scott, J. B., Cognata, A., Qin, X., Camnitz, L. H., and D'Avanzo, D. C., “Linearity characteristics of GaAs HBTs and the influence of collector design,” IEEE Trans. Microw. Theory Tech., vol. 48, pp. 2377–2388, 2000.
[36] Rudolph, M., Doerner, R., Beilenhoff, K., and Heymann, P., “Unified model for collector charge in heterojunction bipolar transistors,” IEEE Trans. Microw. Theory Tech., vol. 50, pp. 1747–1751, July 2002.
[37] Shockley, W., “A unipolar ‘Field-Effect' transistor,” Proc. IRE, vol. 40, Nov. 1952, pp. 1365–1376.
[38] Fernandez-Barciela, M., Tasker, P. J., Demmler, M., and Sanchez, E., “A simplified non quasistatic table based FET model,” 26th Eur.Microw. Conf. Dig., vol. 1, pp. 20–23, 1996.
[39] Gonzalez, G., Microwave Transistor Amplifiers (2nd ed.). Prentice Hall, 1984, p. 61.
[40] Hughes, B. and Tasker, P. J., “Bias-dependence of the MODFET intrinsic model element values at microwave frequencies,” IEEE Trans. Electron Devices, vol. 36, pp. 2267–2273, 1989.
[41] Dambrine, G., Cappy, A., Heliodore, F., and Playez, E., “A new method for determining the FET small-signal equivalent circuit,” IEEE Trans. Microw. Theory Tech., vol. 36, pp. 1151–1159, July 1988.
[42] Parker, A. E. and Mahon, S. J., “Robust extraction of access elements for broadband small-signal FET models,” IEEE Int. Microw. Symp. Dig., pp. 783–786, 2007.
[43] Snider, A. D., “Charge conservation and the transcapacitance element: an exposition,” IEEE Trans. Edu., vol. 38, pp. 376–379, Nov. 1995.
[44] Toorn, R., Paasschens, J. C. J., and Havens, R. J., “A physically based analytical model of the collector charge of III–V heterojunction bipolar transistors,” IEEE Gallium Arsenide Integrated Circuit (GaAs IC) Symp., pp. 111–114, Nov. 2003.
[45] Iwamoto, M., Xu, J., Horn, J., and Root, D. E., “III–V FET high frequency model with drift and depletion charges,” IEEE Int. Microw. Symp., Baltimore, MD, June, 2011.
[46] Root, D. E., Xu, J., Gunyan, D., Horn, J., and Iwamoto, M., “The large-signal model: theoretical and practical considerations, trade-offs, and trends,” IEEE Int. Microw. Symp. parameter extraction strategies for compact transistor models workshop (WMB), Boston, 2009.
[47] Root, D. E. and Fan, S., “Experimental evaluation of large-signal modeling assumptions based on vector analysis of bias-dependent S-parameter data from MESFETs and HEMTs,” IEEE Int. Microwave Symp. Dig., pp. 255–259, 1992.
[48] Ward, D. and Dutton, R., “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. 13, pp. 703–708, Oct. 1978
[49] ,ADS Root FET, Agilent Advanced Design System Manual, nonlinear devices, ch. 3.
[50] Statz, H., Newman, P., Smith, I. W., Pucel, R. A., and Haus, H. A., “GaAs FET device and circuit simulation in SPICE,” IEEE Trans. Electron Devices, vol. 34, pp. 160–169, Feb. 1987.
[51] Smith, I. W., Statz, H., Haus, H. A., and Pucel, R. A., “On charge nonconservation in FETs,” IEEE Trans. Electron Devices, vol. 34, pp. 2565–2568, Dec. 1987.
[52] Root, D. E. “Elements of measurement-based large-signal device modeling,” IEEE Radio and Wireless Conf. (RAWCON) Workshop on Modeling and Simulation of Devices and Circuits for Wireless Commun. Syst., Colorado Springs, Aug. 1998.
[53] Root, D. E., ISCAS tutorial/short course and special session on high-speed devices and modeling,” Sydney, pp. 2.71–2.78, May, 2001.
[54] Root, D. E., Iwamoto, M., and Wood, J., “Device modeling for III–V semiconductors: an overview,” IEEE Compound Semiconductor IC Symp., Oct. 2004.
[55] Aarts, A. C. T., Hout, R.; Paasschens, J. C. J., Scholten, A. J., Willemsen, M., and Klaassen, D. B. M., “Capacitance modeling of laterally non-uniform MOS devices,” IEEE IEDM Tech. Dig., pp. 751–754, Dec. 2004.
[56] Iwamoto, M., Root, D. E., Scott, J. B., Cognata, A., Asbeck, P. M., Hughes, B., and D'Avanzo, D. C., “Large-signal HBT model with improved collector transit time formulation for GaAs and InP technologies,” IEEE Int. Microw. Symp. Dig., Philadelphia, PA, pp. 635–638, June 2003.
[57] Camnitz, L. H., Kofol, S., Low, T. S., and Bahl, S. R., “An accurate, large signal, high frequency model for GaAs HBT's,” IEEE GaAs IC Tech. Dig., pp. 303–306, Nov. 1996.
[58] ,UCSD HBT Model. Available:
[59] ,Agilent Technologies. Available:
[60] Blockley, P.Gunyan, D., and Scott, J. B., “Mixer-based, vector-corrected, vector signal/network analyzer offering 300kHz–20GHz bandwidth and traceable phase response,” IEEE Int. Microw. Symp. Dig., Long Beach, pp. 1497–1500, June 2005.
[61] Verspecht, J., “Calibration of a measurement system for high frequency nonlinear devices,” Ph. D. Dissertation, Dept. ELEC, Vrije Universiteit Brussel, Nov. 1995.
[62] Vandamme, E. P., Grabinski, W., and Schreurs, D., “Large-signal network analyzer measurements and their use in device modeling,” Proc. 9th Int. Conf. Mixed Design of Integrated Circuits and Systems (MIXDES), Wroclaw, 2002.
[63] Schreurs, D., Verspecht, J., Nauwelaers, B., Capelle, A., and Rossum, M., “Direct extraction of the non-linear model for two-port devices from vectorial nonlinear network analyzer measurements,” 27th Eur. Microw. Conf. Proc., pp. 921–926, 1997.
[64] Curras-Francos, M. C., Tasker, P. J., Fernandez-Barciela, M., Campos-Roca, Y., and Sanchez, E., “Direct extraction of nonlinear FET Q-V functions from time domain large signal measurements,” IEEE Microw. and Guided Wave Lett., vol. 10, pp. 531–533, 2000.
[65] Conway, A. M. and Asbeck, P. M., “Virtual gate large-signal model of GaN HFETs,” IEEE Int. Microw. Symp. Dig., pp. 605–608, June 2007.
[66] Jardel, O., DeGroote, F., Reveyrand, T., Jacquet, J. C., Charbonniaud, C., Teyssier, J. P., Floriot, D., and Quere, R., “An electrothermal model for AlGaN/GaN power HEMTs including trapping effects to improve large-signal simulation results on high VSWR,” IEEE Trans. Microw. Theory Tech., vol. 55, pp. 2660–2669, Dec. 2007.
[67] Parker, A. E. and Root, D. E., “Pulse measurements quantify dispersion in pHEMTs,” URSI Int. Symp. on Signals, Systems, and Electronics (ISSSE), Pisa, Sept. 1998, pp. 444–449.
[68] Root, D. E., Xu, J., Horn, J., Iwamoto, M., and Simpson, G., “Device modeling with NVNAs and X-parameters,” IEEE Integrated Nonlinear Microw. and Millimeter-Wave Circuits (INMMIC) Conf., Gotenborg, Apr. 2010.
[69] Tasker, P. J., Demmler, M., Schlechtweg, M., and Fernandez-Barciela, M., “Novel approach to the extraction of transistor parameter from large signa measurements,” 24th Eur. Microw. Conf., pp. 1301–1306, Sept. 1994.