Metal-oxide semiconductor field-effect transistor scaling is following the prediction of the Moore's law enunciated in 1965 [5]. So far, this trend for miniaturization has never been invalided, enabling the industry of semiconductors to cope with the everlasting demand for higher performance at lower cost. However, this scaling becomes increasingly difficult to follow due to inherent process and device performance limitations for technology nodes beyond tents of nm. To stand the pace of downscaling, nonclassical device architectures have been continuously proposed in the ITRS roadmap.

The junctionless field-effect transistor is one of these nanoelectronics devices that is expected to withstand the downscaling of Complementary Metal-Oxide– Semiconductor (CMOS) technology by enabling easier fabrication processes, while allowing high performance. In addition, semiconductor nanowires largely used for label-free biosensing are essentially junctionless FETs without any gate.

Therefore, since the first implementation of junctionless FET nanowires by J. P. Colinge in 2009, growing interest in these devices in different fields of research motivated the authors to write a book dedicated to analytical modeling of double-gate and nanowire junctionless FETs. In contrast to the abundant literature on modeling and compact modeling of inversion-mode MOSFETs, analytical modeling of field-effect transistors without junctions is still following different strategies.

After discussing the advantages and limitations of junctionless field-effect transistors in the first introductory chapter, a thorough overview of published analytical models for double-gate and nanowires configurations is presented in Chapter 2, including the mains assumptions which are introduced.

In Chapter 3 and beyond, the analytical model of the so-called EPFL junctionless field-effect transistor is presented. After discussing the roots ending with a chargebased model valid in all the regions of operation, important features are introduced gradually in Chapters 4–13, each of which targets a specific feature. These topics include nanowire versus double-gate equivalence, technological design-space, junctionless FET performance, short-channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and a revisited model for JFETs. In addition a general mobility extraction technique is proposed.

We suggest readers see Chapter 3 for a general introduction to the charge-based model before proceeding further. This is where the main ideas are introduced that will thus be used in the following chapters.