For more than 40 years, the evolution and growth of very-large-scale integration (VLSI) silicon-based integrated circuits (ICs) have followed from the continual shrinking, or scaling, of the CMOS technology, i.e., of the constituent transistors, or MOSFETs. Remarkably, this scaling of the CMOS technology (Taur and Ning, 2009), which has tracked “Moore’s Law” (Moore (1965): the IC device packing density will double every 18 months) quite well since the 1960s, has not involved any major change in the basic, planar MOSFET structure on bulk silicon or, more recently, on partially depleted (PD) SOI, as shown in Fig. 1.1. This structure has simply been geometrically scaled to gate lengths of Lg ≅ 30 nm, albeit with added complexity to the CMOS fabrication process as well as to the device doping profiles, etc., to control detrimental short-channel effects (SCEs), as described very well in Taur and Ning (2009). Most recently, however, such scaling has been slowed, and even stopped in terms of gate length, mainly because the complex doping profiles required cannot be achieved reliably, or with acceptable yield. The unavoidable randomness of the dopants in the silicon lattice causes, for nanoscale MOSFETs, prohibitive variations in device properties, e.g., the threshold voltage Vt. Indeed, this scaling slow-down is reflected well in Fig. 1.2 by comparison of an exemplary roadmap (SIA, 1994–2011, 2003 ITRS update) projection of high-performance (e.g., microprocessor or MPU) Lg from the Semiconductor Industry Association (SIA) with the actual Lg scaling that has been achieved, indicated by Intel’s MPU scaling results (Natarajan et al., 2008; Auth et al., 2012) superimposed on the projection. Clearly, the technology lags the projection, which has been the general case. The most recent projection (SIA, 1994–2011, 2011 ITRS update) points to Lg = 12.8 nm in 2018 and Lg = 5.9 nm in 2026, whereas the latest reported achievement is minimum Lg = 26 nm in Intel’s 22 nm-node FinFET technology (Auth et al., 2012).