In addition to the planar FD/SOI UTB MOSFET, the quasi-planar (also FD) UTB FinFET, introduced in Chapter 1 and illustrated in Fig. 1.4, is a second primary candidate for future nanoscale CMOS. We discuss in this chapter the features of the FinFET, with reference to the generic UTB-device analyses in Chapter 2, giving its scaling and performance potentials relative to those of the FD/SOI MOSFET. Whereas the basic FD/SOI MOSFET has been under development since the 1980s, the FinFET is relatively new. Although first proposed in 1991 (Hisamoto et al., 1991), the FinFET did not garner much attention until about a decade later because of its unorthodox, nonplanar structure. However, due to Intel’s recent announcement (Auth et al., 2012) that the FinFET will be its basic CMOS device beginning at the 22 nm node, nanoscale FinFET developmental efforts have intensified. The FinFET uses two, or even three, effective gates in concert, and consequently SCEs can be readily controlled with thicker (by ~x2) (fin-)UTBs than those required by the single-gate (SG) FD/SOI MOSFET. The quasi-planar structure, and the uncommon processing thereby implied, can thus be effectively traded off. The measured device characteristics discussed in Sec. 1.1.2, as well as Intel’s noted commitment, reflect the viability of the nanoscale FinFET. We first describe basic features of the generic triple-gate (TG) FinFET, and then use them as a rationale for focusing on the double-gate (DG) mode and as bases for presenting the fundamentals of the FinFET, with insights on optimal/pragmatic device design.

Triple- or double-gate?

The generic FinFET structure in Fig. 1.4 can have, as illustrated in Fig. 4.1, two active gates, on the fin sidewalls, or three active gates, if the top gate is activated by thinning the top insulator on the fin UTB. Considerations of the device electrostatics, parasitic capacitance, and S-D series resistance (Fossum, 2007; Lin et al., 2010), as well as the device processing and integration (Doyle et al., 2003a; Mathew et al., 2007; Auth et al., 2012), must be made for an optimal design tradeoff. In this section, we present insights on the FinFET features that will assist in making a pragmatic choice between DG and TG.