The implementation of the adaptive signal processors (ASPs) depicted in Figures 15.11, 15.12, and 15.15, with some modifications, was as follows. In the case of the linear predictor of Figure 15.11 (in which the training signal is identical with the input signal), the processor consists basically of a 16-tap delay line (Fig. A.1), the outputs of taps 9–16 of which are fed, respectively, to eight amplitude-matching units, each of the type shown in Figure 15.1A. (If the 16 taps of such a delay line are summed by means of precision (1%) resistors, linear interpolation results [compare traces 1 and 2 of Fig. A.2]. If two such units are cascaded, a sigmoid [actually a double parabolic] curve can be generated from a step function [compare traces 1 and 3 of Fig. A.2].)

As indicated in Figure A.1, the analog tapped delay line itself (which has a DC response) consists of two synchronously driven 16-channel analogue multiplexers, which serially transfer, via their interconnected common terminals, the stored voltages between adjacent condenser-based storage (sample-and-hold) units (Barlow 1993, pp. 313–315). The outputs are available both in individual form and in multiplexed form, the latter from the interconnected common terminals of the multiplexers (Fig. A.1). In essence, the unit operates as a “bucket brigade,” as does a charge-transfer device. In the present unit, however, it is voltage rather than charge that is transferred. Figure 15.10 shows a sine wave read out from the tapped delay line at four successively increasing delays.