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10 - RTL Synthesis
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28 - Routing
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29 - Physical Verification and Signoff
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15 - Constraints
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2 - Introduction to Integrated Circuits
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8 - Modeling Hardware Using Verilog
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Dedication
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Contents
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4 - RTL to GDS Implementation Flow
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6 - Testing Techniques
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13 - Technology Library
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11 - Formal Verification
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Acknowledgments
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Part Three - Design for Testability (DFT)
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9 - Simulation-based Verification
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Introduction to VLSI Design Flow
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Preface
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19 - Power-driven Optimizations
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Frontmatter
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Answers
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