Topography after Cu CMP is one of the main issues in constructing reliable Cu interconnects. The wafer level topography is greatly influenced by many polishing properties such as removal non-uniformity and planarization efficiency, and also by many polishing variables. Among the variables, Cu deposition thickness and over polishing time are easily controllable, and closely related to the topography. For a given polishing condition, the topography can be minimized through the optimization of Cu deposition thickness and over polishing time. A model is proposed to account for the correlation between these variables and the wafer level topography. Numerical result of this model shows a strong dependency of optimized Cu deposition thickness and over polishing time on the removal non-uniformity, dishing susceptibility and over plated bump size.