Hostname: page-component-76fb5796d-45l2p Total loading time: 0 Render date: 2024-04-26T19:23:56.911Z Has data issue: false hasContentIssue false

I−V characteristics of co-planar metal-semiconductor-metal nanojunctions

Published online by Cambridge University Press:  15 July 1998

V. Rousset
Affiliation:
CEMES-LOE/CNRS, 29 rue J. Marvig, BP 4347, 31055 Toulouse Cedex, France
C. Joachim*
Affiliation:
CEMES-LOE/CNRS, 29 rue J. Marvig, BP 4347, 31055 Toulouse Cedex, France
T. Ondarçuhu
Affiliation:
CEMES-LOE/CNRS, 29 rue J. Marvig, BP 4347, 31055 Toulouse Cedex, France
B. Rousset
Affiliation:
LAAS/CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex, France
Get access

Abstract

Planar metal/semiconductor/metal (PMSM) junctions buried in a SiO2 layer are fabricated using electron beam lithography on a silicon sample. A technique of jump of pixels is used to obtain different sizes of junctions, the smallest having an inter-electrode distance of 5 nm. The current-voltage characteristics and the variation of the junction conductance with the temperature down to 8 K have been studied. At all sizes and for both polarities, the I−V curves correspond to the reverse characteristic of a metal/semiconductor contact. At low bias voltage, the influence of a thin insulator interfacial layer between the metal and the semiconductor has been pointed out. For these junctions, a non-linear low voltage I−V characteristics is observed before the large voltage thermionic emission regime. For the smallest junctions obtained without interfacial oxide layer, a linear I−V characteristic is recovered at low voltage. Their conductance can be lowered by decreasing the temperature.

Keywords

Type
Research Article
Copyright
© EDP Sciences, 1998

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)