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An analytical study of hot-carrier degradation effects in sub-micron MOS devices

Published online by Cambridge University Press:  29 April 2008

A. K. Singh
A. K. Singh*
Affiliation:
Senior Lecturer Faculty of Engineering and Technology Multimedia University, Melaka Campus, Melaka, Malaysia
*
aks_1993@yahoo.co.uk
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Abstract

In this present communication, we have studied the effect of hot-carrier degradation effects on surface potential, threshold voltage and DIBL of the sub-micron device. We have derived a more accurate model for the threshold voltage in the presence of hot carrier degradation effect. Our model includes a fitting parameter to take care of short channel effects. The validity of our model is verified by the MINIMOS simulator results. Our analysis predicts that the minimum potential position along the channel is not affected by the sign of the hot carrier induced localized interface charge density and always occurs in damage free region. DIBL effect is more pronounced in submicron devices in the presence of the hot carrier degradation effect.

Keywords

Type
Research Article
Information
The European Physical Journal - Applied Physics , Volume 42 , Issue 2 , May 2008 , pp. 87 - 94
Copyright
© EDP Sciences, 2008

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