A review is presented of Synchrotron X-ray Topography and KOH etching studies carried out on n type 4H-SiC offcut substrates before and after homo-epitaxial growth to study defect replication and strain relaxation processes and identify the nucleation sources of both interfacial dislocations (IDs) and half-loop arrays (HLAs) which are known to have a deleterious effect on device performance. We show that these types of defects can nucleate during epilayer growth from: (1) short segments of edge oriented basal plane dislocations (BPDs) in the substrate which are drawn by glide into the epilayer; and (2) segments of half loops of BPD that are attached to the substrate surface prior to growth which also glide into the epilayer. It is shown that the initial motion of the short edge oriented BPD segments that are drawn from the substrate into the epilayer is caused by thermal stress resulting from radial temperature gradients experienced by the wafer whilst in the epi-chamber. This same stress also causes the initial glide of the surface half-loop into the epilayer and through the advancing epilayer surface. These mobile BPD segments provide screw oriented segments that pierce the advancing epilayer surface that initially replicate as the crystal grows. Once critical thickness is reached, according to the Mathews-Blakeslee model , these screw segments glide sideways under the action of the mismatch stress leaving IDs and HLAs in their wake. The origin of the mismatch stress is shown to be associated with lattice parameter differences at the growth temperature, arising from the differences in doping concentration between substrate and epilayer.