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Wafer Thinning for Monolithic 3D Integration

Published online by Cambridge University Press:  01 February 2011

A. Jindal ,
J.Q. Lu ,
Y. Kwon ,
G. Rajagopalan ,
J.J. McMahon ,
A.Y. Zeng ,
H.K. Flesher ,
T.S. Cale  and
R.J. Gutmann
A. Jindal
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York-12180
J.Q. Lu
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York-12180
Y. Kwon
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York-12180
G. Rajagopalan
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York-12180
J.J. McMahon
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York-12180
A.Y. Zeng
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York-12180
H.K. Flesher
Affiliation:
Aptek Industries, Inc., 414-F Umbarger Road, San Jose, California-95111
T.S. Cale
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York-12180
R.J. Gutmann
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York-12180
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Abstract

A three-step baseline process for thinning of bonded wafers for applications in threedimensional (3D) integration is presented. The Si substrate of top bonded wafer is uniformly thinned to ~35 μm by backside grinding and polishing, followed by wet-etching using TMAH. No visible changes at the bonding interface and damage-free interconnect structures are observed after the thinning process. Both mechanical and electrical integrity of the bonded pairs are maintained after the three-step baseline thinning process, with electrical tests on wafers with multi-level copper interconnect test structures showing only a slight change after bonding and thinning. This thinning process works well for Si removal to an etch-stop layer, although present process uniformity is not adequate to thin bulk Si substrates. Other issues such as wafer breakage and edge chipping during Si thinning and their possible solutions are also addressed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 766: Symposium E – Materials, Technology and Reliability for Advanced Interconnects and Low-k Dielectrics - 2003 , 2003 , E5.7
Copyright
Copyright © Materials Research Society 2003

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