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Voltage, Fluence, and Polarity Dependence of Trap Generation Inside of Thin Silicon Oxide Films*

Published online by Cambridge University Press:  22 February 2011

Ronald S. Scott  and
David J. Dumin
Ronald S. Scott
Affiliation:
CSDRR, ECE Dept, Clemson Univ., Clemson, SC 29634
David J. Dumin
Affiliation:
CSDRR, ECE Dept, Clemson Univ., Clemson, SC 29634
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Abstract

The tunnelling front model has been used to obtain the spatial distribution of high-voltage, stress generated traps inside of MOS capacitors. It was found that the number of traps created by high voltage stress was proportional to the cube root of the fluence through the oxide during the stress. Measurement of the trap generation rate indicated that fewer traps were being created as higher amounts of charge were passed through the oxide. Further tests indicated that there was a voltage dependence to the trap generation which was independent of stress polarity.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 284: Symposium G – Amorphous Insulating Thin Films , 1992 , 293
Copyright
Copyright © Materials Research Society 1993

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Footnotes

**

Supported by an SRC Educational Alliance Graduate Fellowship

*

Supported by the Semiconductor Research Corporation

References

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