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Ultra Thin High Quality Ta2O5 Gate Dielectrics Prepared by In-situ Rapid Thermal Processing

  • H. F. Luan (a1), S. J. Lee (a1), C. H. Lee (a1), A. Y. Mao (a1), R. Vrtis (a2), D. Roberts (a2) and D. L. Kwong (a1)...

Abstract

In this paper, ultra thin CVD Ta2O5 stacked gate dielectrics (Teq∼14Å-22Å) was fabricated by in-situ RTP processing. The leakage current of Ta2O5 devices is 103× lower leakage current compared to SiO2 of identical thickness for devices with Teq between 18Å-22Å. While Teq<18Å, the leakage current follows same train and J∼10−3A/cm2 for Ta2O5 stacked gate dielectrics with Teq=14Å. Superior interface properties and reliability have been obtained.

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[2] Park, D. etal., IEEE Electron Device Letter, 19, 441, 1998.10.1109/55.728906
[3] Park, D. et al., IEDM'98, p.381,1998.
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[5] Kim, B.Y. et al., IEDM'97, p. 463,1997.
[6] Son, K.A. et al., J. Vac. Sci. Tech., A16, p. 1670, 1998 10.1116/1.581140

Ultra Thin High Quality Ta2O5 Gate Dielectrics Prepared by In-situ Rapid Thermal Processing

  • H. F. Luan (a1), S. J. Lee (a1), C. H. Lee (a1), A. Y. Mao (a1), R. Vrtis (a2), D. Roberts (a2) and D. L. Kwong (a1)...

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