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Stress-Induced Voiding Vs Temperature and Passivation Thickness IN AI-0.5%Cu-2%Si, AI-0.5%Cu AND Al-i%Si

Published online by Cambridge University Press:  21 February 2011

T. D. Sullivan  and
L. A. Miller
T. D. Sullivan
Affiliation:
IBM Technology Products, Essex Junction, VT 05452
L. A. Miller
Affiliation:
IBM Technology Products, Essex Junction, VT 05452
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Abstract

Stress-induced voiding in microelectronics chips has been reported to exhibit a variety of dependencies on temperature and on passivation stress. The dependence of line failure is reported here at four different temperatures (150, 225, 285, and 315 °C) for AI-0.5%Cu-2%Si, AI-0.5%Cu and AI-1%Si lines with passivation thicknesses (silicon oxide or silicon nitride) ranging from 0.1 to 2.5 times the metal thickness. Failure distributions change in a complex manner with changing passivation thickness, and with temperature for a specific passivation thickness, raising questions on the validity of using the conventional median time to failure (t50) and lognormal slope (σ) to project field failure rates from data generated by accelerated life testing.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 309: Symposium M2 – Materials Reliability in Microelectronics III , 1993 , 169
Copyright
Copyright © Materials Research Society 1993

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