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Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

  • Dechao Guo (a1), Kathryn Schonenberg (a2), Jie Chen (a3), Daniel Jaeger (a4), Pranita Kulkarni (a5), Unoh Kwon (a6), Yue Liang (a7), Joyce Liu (a8), Liyang Song (a9), Franck Arnaud (a10), Huiming Bu (a11), Michael Chudzik (a12), William K Henson (a13), Philip J Oldiges (a14), Melanie Sherony (a15), An Steegen (a16), Voon-Yew Thean (a17) and Mukesh Khare (a18)...

Abstract

For the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

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Keywords

Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

  • Dechao Guo (a1), Kathryn Schonenberg (a2), Jie Chen (a3), Daniel Jaeger (a4), Pranita Kulkarni (a5), Unoh Kwon (a6), Yue Liang (a7), Joyce Liu (a8), Liyang Song (a9), Franck Arnaud (a10), Huiming Bu (a11), Michael Chudzik (a12), William K Henson (a13), Philip J Oldiges (a14), Melanie Sherony (a15), An Steegen (a16), Voon-Yew Thean (a17) and Mukesh Khare (a18)...

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