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Strained Channel Transistor Using Strain Field Induced By Source and Drain Stressors

Published online by Cambridge University Press:  17 March 2011

Yee-Chia Yeo ,
Jisong Sun  and
Eng Hong Ong
Yee-Chia Yeo
Affiliation:
Silicon Nano Device Lab, Dept. of Electrical & Computer Engineering, National University of Singapore, Singapore, 117576
Jisong Sun
Affiliation:
Silicon Nano Device Lab, Dept. of Electrical & Computer Engineering, National University of Singapore, Singapore, 117576
Eng Hong Ong
Affiliation:
Silicon Nano Device Lab, Dept. of Electrical & Computer Engineering, National University of Singapore, Singapore, 117576
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Abstract

We perform a theoretical evaluation of the strain field in a p-channel transistor with silicongermanium (Si1−yGey) stressors in the source and drain regions. The strain field comprises a lateral compressive strain component and a vertical tensile strain component. The lateral strain component is larger in magnitude and more uniformly distributed as compared to the vertical strain component. The impact of transistor design parameters, such as the Ge mole fraction y in the stressors, the spacing L between stressors, the stressor depth, and the raised stressor height, on the strain field are investigated. Hole mobility enhancement larger than 30% is achievable wth L = 50 nm and y = 0.15. More aggressive mobility enhancement targets may be achievable by reducing the stressor spacing and employing a stressor with a larger lattice mismatch with the Si channel.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 809: Symposium B – High-Mobility Group-IV Materials and Devices , 2004 , B10.4
Copyright
Copyright © Materials Research Society 2004

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References

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