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Straight Wall Bumps for High Lead Count Devices: Photolithography and Physical Properties.

Published online by Cambridge University Press:  21 February 2011

Ivana Milosevic  and
Joerg Jasper
Ivana Milosevic
Affiliation:
EM Microelectronic-Marin SA, CH-2074 Marin/NE, Switzerland
Joerg Jasper
Affiliation:
EM Microelectronic-Marin SA, CH-2074 Marin/NE, Switzerland
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Abstract

This paper will report on a novel photolithographic process suitable for the fabrication of gold bumps on high lead count devices. Utilizing a photosensitive polyimide, straight wall bumps are grown completely recessed within the polyimide layer to a typical height of 25 microns.

The photolithographic step of the bumping process will be described. Good layer uniformity in conjunction with exposure in vacuum hard contact mode leads to practically vertical walls of the opening in the polyimide layer after develop.

Straight wall gold bumps have been electroplated in 30 micron wide openings with a 50 micron centerline spacing. This density is beyond the present spacing capability of TAB in production. The bumping process is no longer the limiting factor in high lead count device fabrication.

Potential residues in the polyimide openings would result in bad bump adhesion strength and high bump contact resistance to the underlying metallization. These two parameters were used for the process optimization.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 154: Symposium K – Electronic Packaging Materials Science IV , 1989 , 425
Copyright
Copyright © Materials Research Society 1989

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References

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