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(Selective) Epitaxial Growth of Strained Si to Fabricate Low Cost and High Performance CMOS Devices

  • R. Loo (a1), R. Delhougne (a1) (a2), P. Meunier-Beillard (a3), M. Caymax (a1), P. Verheyen (a1), G. Eneman (a1) (a2), I. De Wolf (a1), T. Janssens (a1), A. Benedetti (a1), K. De Meyer (a1) (a2), W. Vandervorst (a1) (a2) and M. Heyns (a1)...

Abstract

Tensile strained Si on SiGe Strain Relaxed Buffers (SRB) is an interesting candidate to increase both electron and hole mobility which results in improved device performance. Most of this work was/is based on thick (several μm), step-graded SRBs with or without Chemical Mechanical Polishing (CMP) planarisation. This approach bears several disadvantages such as issues with STI formation in the thick SiGe structure, and considerable self-heating effects due to the lower thermal conductivity of the SiGe material. Further, pMOS improvement requires SRBs with high Ge contents (> 30 %), which complicates device fabrication even more. To overcome these issues, we developed a new and cost efficient type of thin SRB (∼200 nm). The concept is based on the introduction of a thin carbon-containing layer during growth of a constant composition SiGe layer. The process relies on standard Chemical Vapor Deposition epitaxial technology without need for CMP. It is designed to allow both non-selective growth on blanket wafers and selective growth in the active area of structured wafers with Shallow Trench Isolation (STI). The selective epitaxial process for strained Si on thin SRBs proposed here, allows relatively simple and cost-effective fabrication of strained Si layers on existing STI structures without any process modification. Further, it offers a very flexible fabrication scheme to independently improve nMOS and pMOS devices. The SRB quality is comparable to the best reported in literature so far, with 70 % and 53 % mobility enhancements for long channel nMOSFETs on 22 % Ge SRBs grown on blanket and STI patterned wafers, respectively.

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(Selective) Epitaxial Growth of Strained Si to Fabricate Low Cost and High Performance CMOS Devices

  • R. Loo (a1), R. Delhougne (a1) (a2), P. Meunier-Beillard (a3), M. Caymax (a1), P. Verheyen (a1), G. Eneman (a1) (a2), I. De Wolf (a1), T. Janssens (a1), A. Benedetti (a1), K. De Meyer (a1) (a2), W. Vandervorst (a1) (a2) and M. Heyns (a1)...

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