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Relaxed SiGe Layers with High Ge Content by Compliant Substrates

Published online by Cambridge University Press:  01 February 2011

H. Yin ,
R.L. Peterson ,
K.D. Hobart ,
S.R. Shieh ,
T.S. Duffy  and
J.C. Sturm
H. Yin
Affiliation:
Center for Photonics and Optoelectronic Materials and Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
R.L. Peterson
Affiliation:
Center for Photonics and Optoelectronic Materials and Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
K.D. Hobart
Affiliation:
Naval Research Laboratory, Washington, DC 20357
S.R. Shieh
Affiliation:
Department of Geosciences, Princeton University, Princeton, NJ 08544
T.S. Duffy
Affiliation:
Department of Geosciences, Princeton University, Princeton, NJ 08544
J.C. Sturm
Affiliation:
Center for Photonics and Optoelectronic Materials and Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
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Abstract

Relaxed, high Ge content SiGe layers have been realized using stress balance on a compliant borophosphorosilicate glass (BPSG). A 30-nm fully-strained Si0.7Ge0.3 layer was transferred onto a 1 μm BPSG film by wafer-bonding and Smart-cut® processes, after which the continuous Si0.7Ge0.3 film was patterned into small islands to allow for lateral expansion. After the strain in Si0.7Ge0.3 islands was released by the lateral expansion resulting from the flow of the BPSG, a Si0.4Ge0.6 layer was commensurately deposited under compression. Upon equilibrium after an annealing, stress balance was formed between the SiGe films, resulting in a larger in-plane lattice constant than that of relaxed Si0.7Ge0.3. With a thiner (6 nm) Si0.7Ge0.3 starting film, an in-plane lattice constant equivalent to fully-relaxed Si0.45Ge0.55 has been obtained.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 765: Symposium D – CMOS Front-End Materials and Process Technology , 2003 , D4.7/G1.7
Copyright
Copyright © Materials Research Society 2003

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