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Rapid Thermal Processing-Based Heteroepitaxy: Material and Device Challenges

  • J. L. Hoyt (a1), P. Kuo (a1), K. Rim (a1), J. J. Welser (a1), R. M. Emerson (a2) and J. F. Gibbons (a1)...


Material and device challenges for Rapid Thermal Processing (RTP) of heterostructures are discussed, focusing on RTP-based epitaxy in the Si/Si1−xGex system. While RTP-based heteroepitaxy offers enhanced processing flexibility, it also poses significant challenges for temperature measurement and control. Several examples of Si/Si1−xGex device structures are discussed from the point of view of the sensitivity of device parameters to variations in layer thickness and composition. The measured growth kinetics for Si and Si1−xGex are then used to estimate growth temperature tolerances for these structures. Demanding applications are expected to require temperature control and uniformity to within 0.5°C.

Future research challenges include the fabrication of structures with monolayer thickness control using self-limited growth techniques. Atomic layer epitaxy (ALE) is a well-known example of such a growth technique. In ALE, the wafer is cyclically exposed to different reactants, to achieve layer-by-layer growth. An RTP-based atomic layer epitaxy process, and its application to the growth of CdTe films, is briefly discussed. The extension to Column IV alloys follows readily. The RTP-based process enables self-limited growth for precursor combinations for which isothermal ALE is not feasible.



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Rapid Thermal Processing-Based Heteroepitaxy: Material and Device Challenges

  • J. L. Hoyt (a1), P. Kuo (a1), K. Rim (a1), J. J. Welser (a1), R. M. Emerson (a2) and J. F. Gibbons (a1)...


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