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Rapid Thermal Processes for Future Nanometer MOS Devices

Published online by Cambridge University Press:  10 February 2011

John R. Hauser
John R. Hauser*
Affiliation:
ECE Department, North Carolina State University, Raleigh, NC 27695, hauser@eos.ncsu.edu
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Abstract

Scaling of MOS devices is projected to continue down to device dimensions of at least 50 nm. However, there are many potential roadblocks to achieving such dimensions and many standard materials and front-end processes which must be significantly changed to achieve these goals. The most important areas for change include (a) gate dielectric materials, (b) gate contact material, (c) source/drain contacting structure and (d) fundamental bulk CMOS structure. These projected changes are reviewed along with possible applications of rapid thermal processing to achieving future nanometer scale MOS devices.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 525: Symposium W – Rapid Thermal & Integrated Processing VII , 1998 , 171
Copyright
Copyright © Materials Research Society 1998

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References

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