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Rapid Optimization of Pentacene Buffer for Rubrene Thin Film Transistors by Using Combinatorial MBE

Published online by Cambridge University Press:  26 February 2011

Masamitsu Haemori
Affiliation:
haemori@oxide.msl.titech.ac.jp, Tokyo Institute of Technology, Materials and Structures Laboratory, 4259 Nagatsuta, Yokohama, N/A, 226-8503, Japan, +81-45-924-5314, +81-45-924-5377
Jun Yamaguchi
Affiliation:
koinuma1@oxide.msl.titech.ac.jp, Tokyo Institute of Technology, Materials and Structures Laboratory, Japan
Seiichiro Yaginuma
Affiliation:
koinuma1@oxide.msl.titech.ac.jp, Tokyo Institute of Technology, Materials and Structures Laboratory, Japan
Kenjji Itaka
Affiliation:
koinuma1@oxide.msl.titech.ac.jp, The University of Tokyo, Graduate School of Frontier Sciences, Japan
Hideomi Koinuma
Affiliation:
koinuma1@oxide.msl.titech.ac.jp, NIMS-COMET, Japan
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Abstract

By means of insertion of thin pentacene buffer layer, we have succeeded in the fabrication of highly c-axis oriented rubrene (5,6,11,12-tetraphenylnaphthacene) thin films and their field effect transistors (FETs). In the case without pentacene buffers, only amorphous rubrene films were obtained and their FETs did not show operation. After optimization of pentacene buffer by using combinatorial thickness-gradient method, we obtained the crystalline rubrene thin films and their FETs showed p-type operation with a mobility of 0.05 cm2/V·s and an on-off ratio of 106.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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