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Post-Anneal Stress Reduction of 200 mm Silicon Wafers in Single Wafer Rapid Thermal Annealing

  • Tsuyoshi Setokubo (a1), Eiichi Nakano (a1), Kazuo Aizawa (a1), Hidekazu Miyoshi (a1), Jiro Yamamoto (a1), Takashi Fukada (a2) and Woo Sik Yoo (a2)...

Abstract

In every wafer processing step wafer stress management is extremely important for advanced device manufacturing. Thermally induced stress on device wafers has a large impact on lithography and affects device yield. Thermally induced stress during rapid thermal annealing (RTA) steps in high density 512MB DRAM device fabrication was investigated using a lamp-based (cold wall) RTA system and compared to results using a furnace-based (hot wall) single wafer RTA system. Compared to the lamp-based (cold wall) system, RTA in a furnace-based (hot wall) system was found to be very effective in suppressing thermally induced stress and increasing device yield due to superior pattern transfer characteristics in lithography.

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Post-Anneal Stress Reduction of 200 mm Silicon Wafers in Single Wafer Rapid Thermal Annealing

  • Tsuyoshi Setokubo (a1), Eiichi Nakano (a1), Kazuo Aizawa (a1), Hidekazu Miyoshi (a1), Jiro Yamamoto (a1), Takashi Fukada (a2) and Woo Sik Yoo (a2)...

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