Hostname: page-component-76fb5796d-vfjqv Total loading time: 0 Render date: 2024-04-25T22:24:58.623Z Has data issue: false hasContentIssue false
  • English
  • Français

Post-Anneal Stress Reduction of 200 mm Silicon Wafers in Single Wafer Rapid Thermal Annealing

Published online by Cambridge University Press:  17 March 2011

Tsuyoshi Setokubo ,
Eiichi Nakano ,
Kazuo Aizawa ,
Hidekazu Miyoshi ,
Jiro Yamamoto ,
Takashi Fukada  and
Woo Sik Yoo
Tsuyoshi Setokubo
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Eiichi Nakano
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Kazuo Aizawa
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Hidekazu Miyoshi
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Jiro Yamamoto
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Takashi Fukada
Affiliation:
WaferMasters, Inc. 246 East Gish Road, San Jose, CA 95112, U.S.A.
Woo Sik Yoo
Affiliation:
WaferMasters, Inc. 246 East Gish Road, San Jose, CA 95112, U.S.A.
Get access

Abstract

In every wafer processing step wafer stress management is extremely important for advanced device manufacturing. Thermally induced stress on device wafers has a large impact on lithography and affects device yield. Thermally induced stress during rapid thermal annealing (RTA) steps in high density 512MB DRAM device fabrication was investigated using a lamp-based (cold wall) RTA system and compared to results using a furnace-based (hot wall) single wafer RTA system. Compared to the lamp-based (cold wall) system, RTA in a furnace-based (hot wall) system was found to be very effective in suppressing thermally induced stress and increasing device yield due to superior pattern transfer characteristics in lithography.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 810: Symposium C – Silicon Front-End Junction Formation-Physics and Technology , 2004 , C5.10
Copyright
Copyright © Materials Research Society 2004

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Timans, P., Nenyei, Z. and Burger, R., “Device Scaling Drives Pattern Effect Solutions”, Solid State Technology, 45 No. 5 (2002) 67.Google Scholar
2. Niess, J., Nényei, Z., Lerch, W. and Paul, S., “Pattern Effects during Spike Annealing of Ultra-Shallow Implants”, Proceeding of Advanced Short-Time Thermal Processing for Si-Based CMOS Devices, (Electrochemical Soc. Proc. 2003-24, Paris, 2003) pp.11–16.Google Scholar
3. Yoo, W.S., Fukada, T., Kuribayashi, H., Kitayama, H., Takahashi, N., Enjoji, K. and Sunohara, K., “Single Wafer Furnace and Its Thermal Processing Applications”, Jpn. J. Appl. Phys. Lett. Vol. 39 (2000) No. 7A, L694.Google Scholar
4. Yoo, W.S., Fukada, T., Kuribayashi, H., Kitayama, H., Takahashi, N., Enjoji, K. and Sunohara, K., “Design of Single-Wafer Furnace and Its Rapid Thermal Processing Applications”, Jpn. J. Appl. Phys. Vol. 39 (2000) 6143.Google Scholar
5. Yoo, W.S., Yamazaki, T. and Enjoji, K., “Thermal Processing in a Single Wafer Rapid Thermal Furnace”, Solid State Technology, 43 No. 7 (2000) 223.Google Scholar
6. Dornberger, E., Temmler, D. and Ammon, W. von, “Defects in Silicon and Their Impact on DRAM Device Characteristics”, J. Electrochem. Soc. 149 (4) (2002) G226–G231.Google Scholar
7. Setokubo, T., Nakano, E., Aizawa, K., Miyoshi, H., Yamamoto, J., Fukada, T. and Yoo, W.S., “Significant Improvement in Device Performance of Advanced Dynamic Random Access Memory by Hot Wall-Based Single Wafer Rapid Thermal Annealing”, Proceeding of Advanced Short-Time Thermal Processing for Si-Based CMOS Devices II, (Electrochemical Soc. Proc. 2004-01, San Antonio, 2004) pp.135–144.Google Scholar