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Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

  • J.-Q. Lu (a1), G. Rajagopalan (a2), M. Gupta (a2), T.S. Cale (a2) and R.J. Gutmann (a2)...

Abstract

Monolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

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Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

  • J.-Q. Lu (a1), G. Rajagopalan (a2), M. Gupta (a2), T.S. Cale (a2) and R.J. Gutmann (a2)...

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