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A Novel Low Temperature Self-Aligned Ti Silicide Technology for Sub-0.18 μm CMOS Devices

Published online by Cambridge University Press:  10 February 2011

L. P. Ren
Affiliation:
Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA90095-1594, ren@ee.ucla.edu
P. Liu
Affiliation:
Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA90095-1594, ren@ee.ucla.edu
G. Z. Pan
Affiliation:
Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA90095-1594, ren@ee.ucla.edu
Jason C. S. Woo
Affiliation:
Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA90095-1594, ren@ee.ucla.edu
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Abstract

A novel low temperature self-aligned Ti silicidation with Ge+ pre-amorphization implant (PAI) is presented. Compared to conventional high temperature PAI silicidation, the advantages of Ti salicidation at temperatures below the recrystallization of a pre-amorphized layer are: (1) C49 TiSi2 silicide formation occurs only in the pre-amorphized layer so that the silicide depth can be well controlled, forming a very sharp interface between the silicide and the Si substrate; (2) Ti just reacts with the amorphous layer, avoiding the so-called bridging issue in which the silicide grows laterally over the isolation or spacer; (3) the effects of metal thickness and substrate doping on silicide formation are suppressed.

Type
Research Article
Copyright
Copyright © Materials Research Society 1998

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References

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