Skip to main content Accessibility help
×
Home

Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs

  • Shuu’ichirou Yamamoto (a1) (a2), Yusuke Shuto (a3) (a2) and Satoshi Sugahara (a3) (a2)

Abstract

We proposed and computationally analyzed a nonvolatile power-gating field programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power-gating (PG). Break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET were proposed, which allows highly efficient PG operations with a fine granularity.

Copyright

References

Hide All
2. Yamamoto, S., Shuto, Y. and Sugahara, S., 71st Autumn Meet. Jpn. Soc. Appl. Phys. (2010) paper 16a-A-2.
3. Yamamoto, S. and Sugahara, S., Jpn. J. Appl. Phys. 48, 043001 (2009).
4. Shuto, Y., Yamamoto, S. and Sugahara, S., J. Appl. Phys. 105, 07C933 (2009) .
5. Yamamoto, S., Shuto, Y. and Sugahara, S., Jpn. J. Appl. Phys. 49, 090204 (2010).
6. Yamamoto, S., Shuto, Y. and Sugahara, S., Electronics Lett. 47, 1027 (2011).
7. Hayakawa, J., Ikeda, S., Matsukura, F., Takahashi, H., and Ohno, H., Jpn. J. Appl. Phys. 44, L587(2005).
8. Berkeley Predictive Technology Model, http://www.eas.asu.edu/∼ptm.
9. Shuto, Y., Yamamoto, S. and Sugahara, S., Jpn. J. Appl. Phys. 51, 040212 (2012).
10. Shuto, Y., Yamamoto, S. and Sugahara, S., 2012 4th IEEE International Memory Workshop (2012).
11. Zhao, W. et al. ., ACM Trans. Embedded Comp. Sys. 9 (2009) Article 14.
12. Suzuki, D. et al. ., 2009 Symp. VLSI Circuits Dig. Tech. Papers (2009) p.80.
13. Xilinx, Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010, p.190.

Keywords

Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs

  • Shuu’ichirou Yamamoto (a1) (a2), Yusuke Shuto (a3) (a2) and Satoshi Sugahara (a3) (a2)

Metrics

Full text views

Total number of HTML views: 0
Total number of PDF views: 0 *
Loading metrics...

Abstract views

Total abstract views: 0 *
Loading metrics...

* Views captured on Cambridge Core between <date>. This data will be updated every 24 hours.

Usage data cannot currently be displayed