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Nitrided Silicon Oxide Gate Dielectrics for Submicron Device Technology

  • G. Lucovsky


The research in this paper is based on an approach to low‐temperature/low‐thermal budget device fabrication that combines plasma and rapid thermal processing, and which has been customized to control separately: (i) the N‐atom bonding chemistry and composition profiles, and (ii) the structural and chemical relaxations necessary for device‐quality performance and reliability for stacked gate structures. Control of N‐atom incorporation at the monolayer level at the crystalline‐Si and polycrystalline‐Si interfaces of field effect transistors, and at alloy levels within the bulk dielectrics has been achieved by combining low‐temperature (∼300°C) plasma‐assisted processes to generate the N‐atom concentration profiles, with low‐thermal‐budget rapid thermal annealing (RTA) to promote chemical and structural relaxations that minimize defects and defect precursors.



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Nitrided Silicon Oxide Gate Dielectrics for Submicron Device Technology

  • G. Lucovsky


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